FSM coding.

[Altera_Forum]

Hi everybody, 

I test the two kinds of FSM on Quartus II: mealy and more, then I check timing analysis on "classic timing analysis" . Anyone explain me why the timing of MOORE FSM is better MEALY FSM, ( it mean MOORE can operate at larger frequency than Mealy)??? Thanks,

[Altera_Forum]

With my full respect to Moore & Mealy for their efforts, I have worked over a decade in FPGA design and never needed to to categorise FSM as such. 

 I design FSM as the logic requires and it may end up with outputs depending on either state only(call it Moore) or state and input(call it Mealy) i.e. probably a mixed Moore Mealy with different proportions...   I will be glad if anybody can tell me if this classification is indeed useful in today's sequential design.   With regard to timing performance, I believe it is more to do with the design itself than being Moore or Mealy since both need be pipelined correctly.

[Altera_Forum]

--- Quote Start ---  I will be glad if anybody can tell me if this classification is indeed useful in today's sequential design.  --- Quote End ---    Unfortunately I can't, I basically share your point of view in this regard. Determining the maximum speed of a FSM block is almost meaningless without considering the adjacent logic, where are the input signals originated from and what's the output's target? If you refer to the Altera FSM templates, the mealy design is involving more complex logic for the output signals and thus can be expected slower.  Some additional remarks related to the basic Mealy/Moore designs as presented in Altera design templates: - They only work correctly, if the input signals have been already synchronized to the clock respectively are originated from the same clock domain - The output signals have glitches, if they are used as direct output signals without additional registers