If the pipeline delays are fixed (i.e. they are independent from pipelined data) you can simply hold the faster pipeline with the appropriate number or clock cycles.
If the delays are variable, you surely have a ready signal coming from each pipeline, so you only need to hold the last stage until both ready signals are asserted.
Anyway the actual solution also depends on the kind of hardware you are dealing with. Infact you may need to redesign the pipeline circuitry in order to provide the required hold functionality.
