Multiple Memory Controllers

[Altera_Forum]

I am using the Stratix II and want to have two Altera DDR2 controllers on the same side of the device. I'm not sure how to go about doing this. Has anyone tried this before?

[Altera_Forum]

Someone else wrote about how to do this in the IP section. Here it is... 

 http://www.alteraforum.com/forum/showthread.php?t=68

[Altera_Forum]

Hi, 

 That existing thread was really concerned with how to make a "single interface" span two opposite sides of a device.  Two controllers on the same side is real easy in Altera devices so long as either: a) They are both operating at the same frequency, so can share the single DLL. b) One of them is operating in PLL capture mode, so doesn't need the DLL.  Altera actually have an application note on this, its not bad, please see: http://www.altera.com/literature/an/an392.pdf  I've attached a Stratix II v71 schematic design of how to do this:) I've set all the core side user signals as virtual pins for ease of example  Regards  Chris

[Altera_Forum]

--- Quote Start ---  Hi,  Two controllers on the same side is real easy in Altera devices so long as either: a) They are both operating at the same frequency, so can share the single DLL. b) One of them is operating in PLL capture mode, so doesn't need the DLL.  Altera actually have an application note on this, its not bad, please see: http://www.altera.com/literature/an/an392.pdf   Chris  --- Quote End ---    If each bus width is larger than 64, then the 2 controllers on the same side is not much easy. Pin assignment to meet the requirement is the first one to deal with. The IP is not flexbile with 2 ddr controller. You may need to manually add the constraints in the Quartus.   And It looks like the device cannot support 2 controllers use dedicated DQS circuit. So the frequency of ddr2 core cannot higher than 166 M(or 200M?)

[Altera_Forum]

Hi htian, 

 Sorry, I don't understand your two statements: 1) If each bus width is larger than 64, then the 2 controllers on the same side is not much easy. Pin assignment to meet the requirement is the first one to deal with. The IP is not flexbile with 2 ddr controller. You may need to manually add the constraints in the Quartus. >> What? Do you mean if the total DQ width of your two controllers is greater than the number of available DQ pins?  2) And It looks like the device cannot support 2 controllers use dedicated DQS circuit. So the frequency of ddr2 core cannot higher than 166 M(or 200M?) >> Again, sorry I don't see your point, I have personally designed StratixII FPGAs with 6 controllers all running at 266MHz, and more recently two controllers at 300MHz on the same side of a single device.  Please clarify your points.

[Altera_Forum]

--- Quote Start ---  Hi htian,  Sorry, I don't understand your two statements: 1) If each bus width is larger than 64, then the 2 controllers on the same side is not much easy. Pin assignment to meet the requirement is the first one to deal with. The IP is not flexbile with 2 ddr controller. You may need to manually add the constraints in the Quartus. >> What? Do you mean if the total DQ width of your two controllers is greater than the number of available DQ pins?  2) And It looks like the device cannot support 2 controllers use dedicated DQS circuit. So the frequency of ddr2 core cannot higher than 166 M(or 200M?) >> Again, sorry I don't see your point, I have personally designed StratixII FPGAs with 6 controllers all running at 266MHz, and more recently two controllers at 300MHz on the same side of a single device.  Please clarify your points.  --- Quote End ---   Hi,   1. no. The bus width of 2 controllers should less than the number of available DQ pins.   First what I said is not to your attached design. We have a design of 2 ddr2 controllers on the same side of EP2S180F1508 (the largest package, I think). Each with 64 bit data bus. so total is 128 bits. In this case, you cannot directly use the constraints generated by the Megawizard for the 2 ddr2 controllers.   2.   The second one is also based on the design I mentioned above. (I am sorry if I did not make it clear). Quartus cannot let you pass if both controllers (each with 64 bit data bus) use DQS mode. The feedback clock mode will limited the highest frequency of controller.  All the controller I mentioned is based on the version less than 6.1 and not "new" high performance controller.   "more recently two controllers at 300MHz on the same side of a single device." how wide of the two controllers?  Thanks,

[Altera_Forum]

Hi Htain, 

 Re your reply,  1. no. The bus width of 2 controllers should less than the number of available DQ pins.  First what I said is not to your attached design. We have a design of 2 ddr2 controllers on the same side of EP2S180F1508 (the largest package, I think). Each with 64 bit data bus. so total is 128 bits. In this case, you cannot directly use the constraints generated by the Megawizard for the 2 ddr2 controllers.  >> So I've just checked, TWO 64bit DDR2 Interfaces do NOT fit on one side of a EP2S180F1508 device in DQS mode! DQS mode only applies to the top or bottom sides of a Stratix II device, and a Stratix II only has 9 x8 DQS groups. As each 64bit interface will require 8 x8 DQS groups, clearly two x64 interface in DQS mode cannot be done!  Hence the only way to get two x64 DDR2 interfaces on one side of a 2S180F1508 is in NON-DQS mode - "Use non-migrateable DQ, DQS, and DM pins" The the design fits, and the constraints generated by the controller can be used! Note this means that the fastest operating frequency is 167MHz  2. The second one is also based on the design I mentioned above. (I am sorry if I did not make it clear). Quartus cannot let you pass if both controllers (each with 64 bit data bus) use DQS mode. The feedback clock mode will limited the highest frequency of controller. >> As stated, TWO 64bit DQS mode controllers simple do not fit on a single side, hence your statement makes no sense.  The 2S180F1508 only has 9 x8 DQS groups (72bit MAX combined interface size), so you can ONLY have say a x32bit and a x48bit interface on the same side of a 2S180! In this case the IP works just fine and the correct constraints are generated.  Also DQS mode interfaces on the same side of a Stratix II design MUST share the DLL, Hence: A) They MUST operate at the same frequency as each other. So IF: B) If the same memory devices are used. C) The same PCB layout constraints are applied. They WILL time the same as each other. In this instance the two or more controllers can actually share the same fedback PLL!  Hope this helps you with your design.  Regards  Monkey:)

[Altera_Forum]

"Hence the only way to get two x64 DDR2 interfaces on one side of a 2S180F1508 is in NON-DQS mode - "Use non-migrateable DQ, DQS, and DM pins" 

The the design fits, and the constraints generated by the controller can be used! Note this means that the fastest operating frequency is 167MHz " >> that is what we did with two x64 DDR2 interface on top side of 2S180F1508. And it already worked (166M) in our board.  Actually I tried to set one with DQS mode, the other with non-DQS mode. It should work but have not tested yet.