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PCI Express Root port with a Nios II

Honored Contributor II

Hello everyone, 


I'm working on a PCI Express Root Port design implemented into a Arria 10 SX device. 


My design must performs data tranfers from the FPGA Root Port to a FPGA End Point as described below :  


[Arria 10 SX - App. User - PCIe HIP Root Port] <-------PCIe-Link-------> [PCIe HIP End Point - App User - Other FPGA] 


I did some researches about the possibility to implemente my own custom driver fully writed in HDL langage. But this idea looks like not reasonable beacause it needs to have a perfect knowledge of the PCI Express stack protocol. 


Consequently, I was interested in the possibility to use a Nios II Soft Processor for the PCI Express Root Port. But, I researched on Internet if a driver was available but I found nothing about it.  


Then, I would like to know if someone have any advices about the writing of a custom driver for PCI Express Root Port implemented into a Nios II. 

Or maybe, about the realization of a PCI Express Root Port implemented into a FPGA device. 




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