Reading HPS Interrupt Controller registers

[DReme]

Hello,

I'm using JTAG MASTER to read registers of controllers in HPS. Only GIC registers always return me zeros. My JTAG Master defined as secure.  I work with Cyclone V SOC.  Does anybody meet the same issue?

[aikeu]

Hi DReme,

May I know more details from you?

1. Can the Jtag Master access other register without problem?

2. What GIC register that you are trying to read?

3. Are you able to write on any of the GIC register？

Thanks.

Regards,

Aik Eu

[DReme]

Hi Aik Eu,
1. Yes, the Jtag Master can access any other register in HPS region.
2. I tried to read all of GIC registers and always I got zeros.
3. No, I didn't try to write.
I suspect that the GIC registers are in some special address space. And this space is not available for access from FPGA fabric.

Regards,
DReme

[aikeu]

Hi DReme,

Are you reading from this address 0xFFFEC100

https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1410068407646.html

Thanks.

Regards,

Aik Eu

[DReme]

Hi Aik Eu,

thank you for your response.

Yes, of course. I tried to read the whole address space beginning from 0xFFFEC100 and 0xFFFED100 too.

Regards,

DReme

[aikeu]

Hi DReme,

I will require some time to test it out on my side. Will feedback to you once I got some findings.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi DReme,

I have prepared the setup and tried it on my side and see that it is returning 0 for the GIC interrupt controller address. I am consulting my team regarding this and will feedback to you again.

Thanks.

Regards,

Aik Eu

[DReme]

Hi Aik Eu,

Thank you.

Regards,

Dreme 

[aikeu]

Hi DReme,

From HPS side, we can read/write the GIC interrupt register,

From FPGA side, we are not able read/write the interrupt register using Quartus system console.

We suspect that there is some secure enablement for the Cyclone V board to do that at the moment which we would like test on it further.

May I know any particular reason from your side to use Jtag master to access read/write on the GIC controller register?

Thanks.

Regards,

Aik Eu

[DReme]

Hi Aik Eu,
I'm a FW engineer. Before I deliver my project to SW team I try to do maximum cover checks, including interrupts from fw to ARM.
Regards,
DReme

[aikeu]

FYI, the access of read/write to the GIC interrupt register in U-boot. 

[aikeu]

Hi DReme,

Thanks for letting me about your scenario.

I am still further querying on this issue, will let you know once I got some new findings.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi DReme,

The address from 0xffd0000 to 0xffff0000 cant be accessed from non-MPU side.

GIC registers are inside MPU registers, which could not be accessed by non-MPU master.

So I think you can check only with HPS side but not from FPGA->HPS which is using the system console through Jtag master

Thanks.

Regards,

Aik Eu

[DReme]

Hi Aik Eu,

Thank you a lot for your effort. 

Regards,

DReme

[aikeu]

FYI, refer to the pic above. The blank area of the non-MPU as compared to the MPU shows access limitation.

Thanks.

Regards,

Aik Eu

[aikeu · Accepted solution]

Hi DReme,

Thanks for your respond. Do give me a good survey if you do get any survey feedback.

I will close this thread for now.

Thanks again.

Regards,

Aik Eu