please help me about the design of Arria V GX pll

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

please help me about the design of Arria V GX pll

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Dear specialist:

My design is shown down, it can run accurately in EP3C120F484I7.

I will transplant it to 5AGXBB3D4F31I5N, I can’t determine if it may be affected by the “Fractionan PLL Phase Alignment Error” listed in <Errata Sheet for Arria V Device> .

The chip AD9653BCPZ-125 is followed by the FPGA and the FCLK is 93MHz.

Please help me，,thanks a lot https://www.alteraforum.com/forum/attachment.php?attachmentid=7547

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