Intel Xeon Phi direct data feed from FPGA via PCI Express

[Valentin_Yakovenkov]

Hello.

Suppose we have a system that consists of a host processor, FPGA card and a Xeon Phi processor connected with a PCI Express fabric. Data is acquired at FPGA card and should be processed at Xeon Phi (one or more nodes) directly.

Is there any simple way to feed data from FPGA card directly to Xeon Phi's memory via PCIe?

Currently I've implemented this for FPGA and DSPs. FPGA card is configured with DSPs BARs and sends data over PCIe memory-write TPLs block-by-block. After each block FPGA sends a memory-write TLP to a dedicated DSP's register to drive an interrupt. DSP's soft catches the interrupt and starts to do it's work over feeded data. This simple scheme gives excellent performance results because of no host-processor in the middle of FPGA and DSPs data path.

It seems that SCIF is implemented the same way to allow device-to-device communications, but it is a bit complicated for FPGA.

[Valentin_Yakovenkov]

After digging mpss-modules source code, I think it's possible to implement own driver sitting at APIC interrupt 5 or 6 (interrupts 0-4 and 7 used by MPSS itself for VNET/etc modules) and doing simple double-buffered direct DMA transfers with our FPGA card.

But I can't find any information about APICI register bits (there is a "magic" comment in the sources about bit 13 of APICICR register must be set to send an interrupt request tu Xeon Phi core). 

Where can I find low-level documentation for Xeon Phi processor describing (at least) it's APIC/DMA registers?

[TaylorIoTKidd]

Valentin,

Have you looked at the Software Developer's Guide (SDG), http://software.intel.com/en-us/articles/intel-xeon-phi-coprocessor-system-software-developers-guide?

Regards
--
Taylor
 

[Valentin_Yakovenkov]

Taylor,

Yes, I have, but this document doesn't describe Knight's Corner registers, it gives only the addresses for them. It has a reference to "SDM Volume 3A System Programming Guide", but that document (chapter 10.6.1, Interrupt Command Register) marks bit 13 as reserved. So, I think Knight Corner's APIC is a little bit different than standard one found in mainstream processors.

May be I don't understand something about APIC's correctly for now, but anyway, I'll try to write own lowlevel driver and a little userspace framework to try to implement direct Phi-FPGA communication task. %)

Thank you.

[TaylorIoTKidd]

I will try and find you more concrete information.

[TaylorIoTKidd]

Valentin,

I found the information but the development team hasn't released it publicly. I'm working on getting it released but don't know how long this will take. These things might happen in a day or a month. 

I'll do my best to let you know the time frame by the end of the week.

Regards
--
Taylor

PS If your company has an existing NDA with Intel, I can get you the information sooner. You can send me an offline email. Nevertheless, I'll do my best to get it released publicly.

[Bedoustani1]

Hi Taylor,

Is the above mentiend information publicly released? If yes, where can I find it?

Yours,

--

Bedoustani

[TaylorIoTKidd]

Bedoustani,

I haven't had any success, not because of any internal resistance but because it is seen as low on the priority list. And, truthfully, I can't see it being bumped higher unless I can provide them with a stronger business/market incentive. To say it another way that makes more sense to us engineers, I need to be able to convince them that by not doing so, they are missing out on a market for current or future sales.

Do you, or anyone else, have any suggestions that I can use to provide them with greater incentive. It doesn't have to be current sales, it can be a potential market assuming development can proceed.

Regards
--
Taylor