Hello all,
As mentioned in previous posts, I have been attempting to communicate with the SSRAM chip provided with the Cyclone III starter kit. I have a state machine that produces the control signals in the sequence described in the timing diagram of the data sheet for this chip. I don't quite know how to use alot of the features in the Quartus II software so I have decided to make my checks the old fashioned way.. with a scope. I noticed that when I look at the bidirectional pins that are connected to the DQ lines of the RAM, regardless of the values I input to these pins, all pins are always high (I have a few tri-state buffers mediating traffic between input pins, output pins, and the bidir pins connected to DQ). It is as though these pins are constantly inputting high values to the FPGA. Is there specific design logic needed to mediate the input and output of bidirectional pins, or is this likely the result of poor timing with the control signals? Thanks.
Andre
