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Cyclone II configuration problem

Altera_Forum
Honored Contributor II
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Dear all, 

I am using an EP2C50F672 Cyclone II FPGA and I am facing problems booting it from the EP2C16.  

All connections with MSEL and related config pins of FPGA are as advised in datasheet. 

The problem is that the FPGA will not start reading from the EP2C16. Configuration and Verification of the EP2C16 works fine. 

However, No DCLK is generated from the FPGA at power up and CS won't go down apart from some spurious pulses in the beginning. 

Anyone seen something similar? 

 

Regards, Stefanos
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Altera_Forum
Honored Contributor II
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I am a little confused. 

 

Are you using the EP2C16 as a boot device? 

Do you mean the EPCS16? 

 

Please clarify. 

 

Then also provide all you interconnections and MSEL connections in a table. 

 

Thanks.
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Altera_Forum
Honored Contributor II
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Dear all, 

we are using the EP2C50672C6 FPGA and the EPCS16 as the boot device. 

We connect  

MSEL0 ----- GND 

MSEL1 ----- GND  

setting for AS 

NCE ----- GND  

N_STATUS --- weak pulled up 

N_CONFIG --- weak pulled up 

CONF_DONE --- weak pulled up 

 

All connections based on Altera datasheets. However, device won't start reading from EPCS at power up. 

 

Contacted a number of people for support and still no luck.
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Altera_Forum
Honored Contributor II
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Check the quality of the Power Supplies. Make sure that there is enough current, and enough bypassing. 

 

Also make sure that the value of the "weak pullups" is not too weak, as some of the signals you are connected to have internal pulldowns and you might not be getting above their trip point? 

 

Also, can you directly JTAG into the Cyclone FPGA and get it runniing correctly? 

Try that first to help isolate the issue between FPGA can run OK and FPGAa cannot config from Prom.
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Altera_Forum
Honored Contributor II
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>>Check the quality of the Power Supplies. Make sure that there is enough current, and enough bypassing. 

3.3V are sourced directly from PCI-X bus which means that there should be no problem. 1.2V are taken from the output of a linear regulator with current capability of 5A. Large enough. 

 

>>Also make sure that the value of the "weak pullups" is not too weak, as some of the >>signals you are connected to have internal pulldowns and you might not be getting >>above their trip point? 

We are using the recommended resistor values from Altera, 10kOhm. 

 

>> Also, can you directly JTAG into the Cyclone FPGA and get it runniing correctly? 

We can configure Cyclone directly with no problems. We can program and verify the EPCS but FPGA will not start reading from the EPCS.
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Altera_Forum
Honored Contributor II
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Hi stefanos, 

Well what I understand from your post you are able to run your FPGA as per your design via .sof(configuring FPGA alone) but unable to do so if you write .pof to EPCS. 

 

Well just check up Assignments->settings->device->configuation settings and uncheck the Compressed bitstream option. Recompile and give it a try. 

 

If your hardware is fine it should work.
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Altera_Forum
Honored Contributor II
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Dear jmaniac 

I know the problem you refer to, we seem to have a more serious problem than that. The FPGA won't generate DCLK at power up and will not try to read from the EPCS even when we drop n_config. Very odd for a device. 

Stefanos
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Altera_Forum
Honored Contributor II
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Hi stefanos, 

Is it possible fot you to upload the Circuit of your FPGA, 

Power connections and Configuration Circuit would be more than 

enough. Well Just incase if we could find someting......
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Altera_Forum
Honored Contributor II
562 Views

Hi, 

 

Apparently something is wrong with AS configuration pins on your board. Are you having the same results on other boards as well? If yes, then try taking look at the AS Mode configuration pins status when you initiate the configuration and when the configuration completes. Are all the signals showing correct state or one/few pins are showing weird state? Try to monitor the status of nCONFIG, nSTATUS, nCE, nCEO and CONF_DONE pins during and after configuration in AS Mode. 

 

I don't know how much it will help, but you could also try followings: 

FPGA Configuration Troubleshooter:  

http://www.altera.com/cgi-bin/ts.pl?fn=configuration 

Debugging Configuration Problems: http://www.altera.com/literature/hb/cfg/cfg_ch11_vol2.pdf 

 

Hope this helps. 

BD
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Altera_Forum
Honored Contributor II
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This happened to me before although for another device, try manually converting your file to pof from sof instead of using the auto generated pof.

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