uClinux MMC SPI Driver

[Altera_Forum]

Just to let everyone know, an MMC SPI Driver for Alteras SPI Core (modified) is in the works.. currently, cards can be recognized, read/write, and even partitioned.. but some bugs are being worked out. If anyone is interested in an early release, let me know....

[Altera_Forum]

--- Quote Start ---  originally posted by hippo@Apr 4 2006, 07:49 PM i am working on it , right now. still cleaning from 2.6.11 to 2.6.12 . <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14030)  --- quote end ---    --- Quote End ---    cool - you can post a diff patch for each stage you go and I&#39;ll quickly test it out for you on my hardware.  It would be nice if kernel.org had a SVN repo; then I could at least tell when the MMC layer changed!

[Altera_Forum]

Sure , I will send you the results for early testing. 

 <div class='quotetop'>QUOTE </div>  --- Quote Start ---  It would be nice if kernel.org had a SVN repo; then I could at least tell when the MMC layer changed![/b]  --- Quote End ---   The kernel.org use "git" for version control. But I didn&#39;t try it yet.

[Altera_Forum]

J, 

I am still working on 2.6.12 . I am checking them again other arch, to find out the problem in nios2 kernel. Will let you know when I have some found.

[Altera_Forum]

It is strange.  

when I set ddr sdram size from 64M to 8M, the page allocation failure did not happen. is it hardware issue?  I will focus on this problem, and will not be available for others. sorry.

[Altera_Forum]

--- Quote Start ---  originally posted by hippo@Apr 5 2006, 09:21 PM it is strange.  when i set ddr sdram size from 64m to 8m, the page allocation failure did not happen. is it hardware issue?  i will focus on this problem, and will not be available for others. sorry. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14082)  --- quote end ---    --- Quote End ---    Hey hippo,l   I&#39;m using a 32M DDR chip; that&#39;s really weird though. So you think it&#39;s a problem with the DDR core itself, maybel ocking up the avalon bus?  <div class='quotetop'>QUOTE </div>  --- Quote Start ---  I will focus on this problem, and will not be available for others. sorry.[/b]  --- Quote End ---    I&#39;m sorry, what do you mean by this?

[Altera_Forum]

I am using ddr sdram of 64M chip (x16) . I changed the ddr size to 8M in ptf for hwselect, and did not change the sof. I will do more testing on this, eg 16M 32M. 

Please try out on yours.  I mean, I will not have time to help others. I have to resolve this issue first.

[Altera_Forum]

ok, i understand; I will try this out to confirm, and I will have more time tomorrow to investigate. I will get bak to you shortly though.

[Altera_Forum]

16M is OK. 

 I just found there is ddr core update 3.3.1 . I got qii and nios2 v6.0 beta , too. I will try out right now.

[Altera_Forum]

I am already using 3.3.1 (it&#39;s been out for some time) - QII 5.1 sp2 and NII 5.1 sp1

[Altera_Forum]

Do you have boards that use sdram instead of ddr?

[Altera_Forum]

Ya, I have a 1C12 and a 2S60 Stratix II Eval board that I can try it on. Unfortunately, I won&#39;t bea ble to try it tonite as I&#39;m working remotely into my board http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

[Altera_Forum]

The problem doesn&#39;t seem to be going away when I set it to 16M. I couldn&#39;t even boot the kernel on 8M, didn&#39;t strip it down enough...

[Altera_Forum]

I wonder if others can help out the tests, 

I am testing with altera cf core to a cf drive of 1GB, formated to fat.  mount -t vfat /dev/hda1 /mnt dd count=1000000 bs=512 if=/dev/zero of=/mnt/z2 free (or df)  it will write a file of 500MB of zero. after the dd write, the next command will have "page allocation" fault with a new kernel.  When I reduce the ddr size in ptf, without change to sof, from 64M to 8M,16M,32M, the problem disappeared.

[Altera_Forum]

What I don&#39;t get is why this is happening with the newer kernels if it&#39;s a hardware issue? It should happen in the older ones, no? 

 This iswhat I think it is; I think the fact that it worked for 32M and not 64M for you doesn&#39;t mean that there is a problem with 64M necessarily. I think it&#39;s very dependant on the kernel build. I use 32M normally, and 16M still gave me a problem. I&#39;m sure if others try this, they will find different numbers. I think it&#39;s something much more fundamental... maybe a byte-alignment issue, something quirky like that.

[Altera_Forum]

I tried ddr core 3.3.1, the result is the same. 

I am back to kernel patch work.

[Altera_Forum]

I tested more boards, with even larger dd count. 

ddr sdram 128MB on 2C20, passed. sdram 32MB on 1C6, passed.  only one new board has the failure, ddr sdram 64MB on 2C8, failed. but reduce hwselect to 32M,16M,8M passed.  I have checked several patches of other arch from kernel.org, and can not find critical update from 2.6.11 to 2.6.12.  The board with problem is PQFP package of cycloneII . It was before I read the SSN guide. I wonder different kernels may have different buffer cache algo, so that 2.6.11 does not trigger the failure. I will check SSN more carefully on that board.

[Altera_Forum]

Interesting; what&#39;s SSN?

[Altera_Forum]

--- Quote Start ---  originally posted by jdhar@Apr 7 2006, 03:49 PM interesting; what&#39;s ssn? <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14119)  --- quote end ---    --- Quote End ---    Cyclone II Simultaneous Switching Noise (SSN) Customer Guidelines (but it is altera confidential. you may check with altera)

[Altera_Forum]

hippo, if it&#39;s hardware, like you may be suggesting, a few things don&#39;t make sense: First, DDR running at 80M is very slow, so I wouldn&#39;t think SSN would be a problem. I have tried it on two boards of the same hardware, and both have the same problem. Secondly, I&#39;m using the 2C35 in a BGA package, so SSN is even less likely. Also, why would it fail just for block device accesses? The CF or MMC doesnt&#39; even DMA into RAM, so it will be much slower. Ethernet on the other hand, does, but that seems to be ok???  

 Also, I ran the DDR tester core on my hardware a long time ago at 100M+ and there were no failures. AND.. why would it work for 32M but not 64M when you change the PTF? The hardware is still the same.  I don&#39;t necessarily think the problem is in the kernel... it might be in the core or the fabric. But I have no idea how to figure this one out, there are too many places to start!

[Altera_Forum]

hippo, I back-ported my MMC driver to 2.6.11, and the problem is gone. This was as suspected since the problem was there without MMC, but I really don&#39;t think it&#39;s hardware. 

 Oh so confusing!

[Altera_Forum]

--- Quote Start ---  originally posted by jdhar@Apr 8 2006, 10:49 AM hippo, i back-ported my mmc driver to 2.6.11, and the problem is gone. this was as suspected since the problem was there without mmc, but i really don&#39;t think it&#39;s hardware.  oh so confusing! <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14138)  --- quote end ---    --- Quote End ---   J, I am checking more kernel patches, up to patch-2.6.10, 2.6.11, 2.6.12 of kernel.org. I will check more boards, and boards qsf setting, too.  One thing to note about high speed logic niose, it is not related to clock freq, but the slew rate and number of nodes which switch at the same time.