Difference between VCCIO and VREF?

[Altera_Forum]

hi,everyone. 

 i just start to use fpga cycloneIII,and i have a question which may be easy to answer. Thank you.   question :is it right that VCCIO just supply the power?for example,if i want to use a bank to interface with a 3.3v device,i could VCCIO=2.5 and make sure VREF==3.3?

[Altera_Forum]

You can omit VREF pins if you are not using any voltage referenced IO standard. In this case you can use VREF pins just like any other IO. VCCIO is the main supply lines, which must be tied to the supply voltage, which is the expected IO supply, e.g., Connect 3.3V to VCCIO for 3.3V IO (using a 3.3V device).

[Altera_Forum]

BD SLS 

Thank you.  IF interface fpga with 2.5v device,VREF must be connected to 2.5V,and VCCIO could be connected to 3.3V, and in this case,IO ports in this bank is 2.5V standard.  Is it right?

[Altera_Forum]

--- Quote Start ---  BD SLS  Thank you.  IF interface fpga with 2.5v device,VREF must be connected to 2.5V,and VCCIO could be connected to 3.3V, and in this case,IO ports in this bank is 2.5V standard.  Is it right?  --- Quote End ---    No. If you want to interface with a 2.5V device you need to connect VCCIO for those banks to 2.5V. VREF is used only for voltage referenced SSTL or HSTL I/O modes, in which case you connect VREF to half the rail normally(example: for VCCIO=2.5V, VREF=1.25V). If you don't use SSTL/HSTL, VREF pins can be used as normal I/Os.

[Altera_Forum]

--- Quote Start ---   If you don't use SSTL/HSTL, VREF pins can be used as normal I/Os.  --- Quote End ---   Make sure you check the device handbook before doing this - I don't know about older devices, but the Stratix IV specifically states that if VREF pins are not used for voltage referencing, they cannot be used as generic I/O (Vol.1, 6-54)

[Altera_Forum]

VREF pins can be shared as IOs with all Cyclone devices, they are dedicated pins with Stratix and Arria.

[Altera_Forum]

Be careful when using the VREF pins as fast I/O on the Cyclones, the VREF pins have a higher capacitance than the regular I/O pins.

[Altera_Forum]

how to configure a VREF pin as IO in cyclone 3 ? 

there are commands line to add to qsf file ?

[Altera_Forum]

Simply assign them as IO. No additional settings required.

[Altera_Forum]

Hi, 

I've red somewhere that 1.25V should be asserted to the VREF pins (with Cyclones III) when using the LVDS standard. However, I do not find anything clear about that in the device familly handbook...  So if I use LVDS signalings with a bank, I must apply 2.5V to VCCIO pins and what about the VREF pins?  Yours faithfully

[Altera_Forum]

The VREF pins aren't used with LVDS. They are only used with some fast single-ended iI/O standards, such as SSTL. 

You can use those pins as regular I/O.