What destroys an FPGA ?

[Altera_Forum]

I have managed to destroy two different boards, over 6 months. And still can't quite seem to figure out what I did wrong.  

 My most recent is a Cyclone III board where "My First FPGA" design no longer runs ( LED 2 doesn't light up ). Also any of the Nios II apps no longer are able to connect.   This all happened after I had an updated pin configuration, so I know:  Clearly it is (l)user error.   What I want to know is can people share there experiences of the dumb things they have done to destroys and FPGA ?  Thanks.

[Altera_Forum]

Historically FPGA's have been fairly robust. But just recently, a co-worker managed to destroy a Cyclone III FPGA by momentarily shorting the 1.2 V supply to 5 V. 

 Although I have never seen an FPGA destroyed, due to incorrect IO configuration, it does stress the part, and with the smaller process geometries used today, it's very conceivable to destroy the IO buffer.  ESD is always a possibility, but again, I haven't seen one fail due to an ESD event either.  Pete

[Altera_Forum]

Actually, I managed to destroy the JTAG configuration port in the Cyclone on one of my old development boards and I'm certain that ESD was the culprit. It was weird because the rest of the chip was fine and could still configure via the eeprom configuration chip, just the JTAG port was dead to my Byte Blaster.

[Altera_Forum]

I plugged the JTAG header in backwards on a Cyclone II DSP board. It overheated and shut down for a few minutes, then revived with no damage. 

 I put a MAX 2 board through the clothes washer, no damage.  A coworker left a Stratix II in IO contention with a RAM chip over the weekend. No damage to either.  I left a DE2 board with LCD display in my slightly hot car for an hour, busted. Go figure.

[Altera_Forum]

If you have a design where you select the unused pins to be "outputs driving ground" and your board actually has those 'unused' pins connected to something other than ground, you can draw a LOT of current. I haven't actually ruined a chip doing this, but I have made them pretty hot. I'm sure if you left it in this state long enough...

[Altera_Forum]

I have seen a Stratix II part that was damaged by over voltage/spikes on the IO pins. 

 It was designed to interface to a PC Parallel port and was destroyed by not ensuring that the data/ctrl pins were driven by 3.3V i.e. There was no buffering between the 5V PC parallel port and the Stratix FPGA!   Needless to say, in future a new cable with a 3.3V buffer was hatily constructed!