Reset process on a XIO1100 PHY

[Altera_Forum]

Hi all, 

 With the XIO1100 documentation, I tried to initialize it with a dev card based on Cyclone II. Unfortunately, I see with my logic analyzer that the signal PHY_STATUS is never de-asserted in order to complete the power and refclk stability. First of all, I think that the refclk signal is driven by on board oscillators isn'it ? ('cause I don't find any PIN assignation on this signal for the FPGA)  So, which reset have I to de-assert in order for the PHY to complete its first initialization & de-assert my PhyStatus signal ? (PCIE ? LOCAL ? PHY ?) So what is the first process or the cause of my issue ?  Thank for an answer.  Cheers...

[Altera_Forum]

It's okay I resolved the problem. In fact I have to assert the /RESET before the XIO signals me its stable power and rxclk by de-asserting PHYSTATUS. The XIO data sheet is especially bad and unprecise.. No chronograms at all for the initialisation, etc... 

 but does someone know, once the XIO ready, when does the de-assertion of rx_elecidle? Or if it's because a special or wrong mode in the board that mine is never de-asserted (=no symbol lock) ?  Thank you and best regards.

[Altera_Forum]

Please be aware that all the problems I had with the XIO 1100 are now resolved and if someone's got a question, I'll answer with pleasure. ;)

[Altera_Forum]

--- Quote Start ---  Please be aware that all the problems I had with the XIO 1100 are now resolved and if someone's got a question, I'll answer with pleasure. ;)  --- Quote End ---     ng       I had a problem with XIO1100. Traininjg Sequence is not getticompleted.  My device is sending TS1 frames, but they are not received correctly by host. TI PHY is sending only 2 byte ( BC-F7 ) twice and then one full TS1 but with 3rd,4th byte and last 2 bytes corrupted instead of 3 TS1 correct frames. This is repeated every 3 TS1 frames.    Did you face this/similar problem ?   Thanks, Vinayak.