DCFIFO and DMA for transfering data to an SRAM

[Altera_Forum]

Hi, 

 I have a dcfifo in my design (wich is interfacing two different clocks domains...)... I want to copy the FIFO (not in SOPC) content on an SRAM memory using the DMA (from SOPC). Does anyone know how to do it ?  I have a look on the an473 (http://www.altera.com/literature/an/an473.pdf) (using DCFIFO for data transfer between Asynchronous Clock Domains). This AN don't explain how to do it with a DMA module. In the DMA docs, I don't find anything about using DMA with a FIFO... Someones suggest me the use of an "Avalon to External Bus Bridge", but this IP Block (available from university program) seems to work as an Handshake Protocol (as mentioned in the AN473)  So, is it possible to use a DMA with the Avalon to External Bus Bridge ? How can I interface a FIFO with a memory block (SRAM) using a DMA ?  Many thanks.

[Altera_Forum]

Hello, 

 I'm having a problem in the compilation when the RX FIFO depth and TX FIFO depth are different.  It seems that there is a bug when generating the VHDL code:  If TX FIFO depth is 8 bytes and RX FIFO depth is 16 bytes: Error (10344): VHDL expression error at slot1_uart.vhd(1562): expression has 4 elements, but must have 3 elements  If TX FIFO depth is 8 bytes and RX FIFO depth is 32 bytes: Error (10344): VHDL expression error at slot1_uart.vhd(1562): expression has 5 elements, but must have 3 elements  And so on..   If the two depths are the same, no error occurs.  Is there anyone experiencing the same problem?  Thank you.