Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20707 Discussions

Using Tri-state buffer on bus

Altera_Forum
Honored Contributor II
1,266 Views

Hello,  

 

I have been using the tristate buffer (from primitives/buffer folder) to control a byte wide bus. I have noticed a number of warnings while compiling and was wondering if this feature was designed for a single line, or if it can handle larger bus lines? If not, what is the alternative for this case? Thanks.  

 

Andre
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
360 Views

I guess, you are talking of bidirectional buffer in schematic entry. It can also be used with busses, as many other elements too. I wouldn't expect that the warnings are related to connecing a bus to the buffer.

0 Kudos
Altera_Forum
Honored Contributor II
360 Views

Since there is no physical tristate bus inside an FPGA the Quartus software has to generate a multiplexer logic that replaces the logical tristate bus. Maybe the warnings are caused by this multiplexer logic?

0 Kudos
Altera_Forum
Honored Contributor II
360 Views

I have changed a few things and the warnings have disappeared. I guess I misinterpreted what was meant by the warnings. Thanks for your input.

0 Kudos
Reply