Cyclone II: how to delay output to pin?

[Altera_Forum]

Is there any way to delay the data output to a pin? I have tried all possible settings in Quartus II and the only way to delay (around 4ns) seems to be to use LCELLs. Also, i'm seeing that an input pin delay is 5.5ns. I need to lower this input delay to 3.5 ns. Any ideas?

[Altera_Forum]

What is it you are trying to do? My recommendation would be to start using the TimeQuest timing analyzer as it gives you more control over these timing settings. You specify your setup and hold requirements for the input pins. The fitter will then place your logic cells appropriately to meet your timing requirements.

[Altera_Forum]

First you need to follow jakobjones' advice. Fully constrain the setup and hold requirements for both inputs and outputs, preferably using set_input_delay and set_output_delay -max and -min in TimeQuest. 

 In addition to giving the Fitter the I/O timing constraints, you might need to set "Optimize hold timing" to "All paths" on the "Fitter Settings" page of the Settings dialog box. The "Description" field in the dialog box in QII 8.0 sounds like "All paths" is no longer necessary for TimeQuest, but in the past you had to use "All paths" to get this optimization to apply to hold for I/O constrained with set_input_delay -min and set_output_delay -min. "All paths" is still needed for certain kinds of Classic Timing Analyzer I/O constraints.  If the amount of additional delay needed to satisfy the set_output_delay -min requirement (corresponds to the minimum tco) isn't too much and if the output register is not in the I/O cell, the hold optimization will result in routing delay being inserted.  The Fitter will try to set the input and output delay chains to an appropriate value to meet both setup and hold requirements, but you might need to control these delay chains manually through the Assignment Editor to increase your output delay and reduce your input delay. To slow the output in Stratix III, for example, use the "D5 Delay" or the "D6 Delay" settings (a figure in the Stratix III handbook shows where D5 and D6 delay chains are in the I/O structure). The Assignment Editor will call this delay something else for other device families.  If you need to create a larger minimum delay than the Fitter does well by automatically inserting routing, then manually inserting a chain of LCELLs might be the best way. Be sure to analyze the timing for all timing models. You always should do this, but it is even more important when trying to create a minimum delay with logic resources that might have a lot of variation over process/voltage/temperature. You might need to enable "Optimize fast-corner timing" in the Fitter Settings to get good results with the fast timing model.  If you can phase shift the clock used by the I/O registers (even if you have to use an additional PLL output for just this), then adjusting the clock can let you fine tune the tradeoff between setup and hold.

[Altera_Forum]

--- Quote Start ---  My recommendation would be to start using the TimeQuest timing analyzer as it gives you more control over these timing settings. You specify your setup and hold requirements for the input pins. The fitter will then place your logic cells appropriately to meet your timing requirements.  --- Quote End ---    I'm currently using the assignment editor in an attempt to increase output signal delay and lower input signal delay but no change in timing can be measured. I have tried every possible setting but the signal timings will not budge.   Is it not possible to configure input and output timing when using the classical timing analyzer? I'm using Quartus II 7.1

[Altera_Forum]

Thanks Brad. I will look into your suggestions. I have used a PLL output to phase shift some signals but i have no more PLL outputs available so i'm trying to affect I/O timings by configuring the IOEs. It appears not to work at all. I have used LCELLs in the past but since the timings may change with temperature, chip batch etc it seems unreliable.  

 How much can the LCELL delay change between chips? I need to achieve some +/- 4ns delay or more so if the LCELL timings change with less than 25% i should be good.

[Altera_Forum]

--- Quote Start ---  I have used LCELLs in the past but since the timings may change with temperature, chip batch etc it seems unreliable.   How much can the LCELL delay change between chips?  --- Quote End ---     This is why I said to be sure to analyze the timing for all timing models. That will cover the timing variation over PVT.

[Altera_Forum]

--- Quote Start ---  Is it not possible to configure input and output timing when using the classical timing analyzer? I'm using Quartus II 7.1  --- Quote End ---     Even though TimeQuest has been enhanced since QII 7.1, it was the preferred timing analyzer for new designs even then. Even in QII 8.0 you may still use the Classic Timing Analyzer for device families that allow it. As I mentioned before, pay attention to what the "Description" field in the Fitter Settings dialog box says for "Optimize hold timing". The description might not have been as detailed about the behavior in QII 7.1, but the 7.1 behavior with the Classic Timing Analyzer was probably the same as described for 8.0 (the behavior with TimeQuest is what I remember changing).  This is the QII 8.0 "Description" text:    --- Quote Start ---  Allows the Fitter to optimize hold time by adding delay to the appropriate paths. The Optimize Timing option must be turned on in order for this option to work. If you are using the Classic Timing Analyzer and specify the I/O Paths and Minimum tpd Paths setting, which is the default setting, the Fitter optimizes hold timing only for the following assignments: th assignments from an I/O pin to a register, Minimum tco assignments from a register to an I/O pin, and Minimum tpd assignments from an I/O pin or register to an I/O pin or register. All other I/O pin assignments, such as Minimum Delay, Input Minimum Delay, and Output Minimum Delay, are not optimized. If you are using the TimeQuest Timing Analyzer, and specify the I/O paths and Minimum tpd Paths setting, which is the default setting, all assignments involving I/O pins are optimized. Specifying the All Paths setting directs the Fitter to optimize the hold time of all paths. Turning off this option directs the Fitter not to optimize the hold time of any paths.  --- Quote End ---  

[Altera_Forum]

--- Quote Start ---  How much can the LCELL delay change between chips? I need to achieve some +/- 4ns delay or more so if the LCELL timings change with less than 25% i should be good.  --- Quote End ---     The timing models cover the timing range for all contributions to variation from process, voltage, and temperature. The reported timing does not distinguish between each contributor.  The "change between chips", which is in the process variation, includes the possibility that the chips will actually be as fast as the fastest speed grade even if the chips are marked with a slower speed grade. That's why TimeQuest does not include the speed grade in the name of the fast operating conditions; it uses the same fast-model timing for all speed grades. In order to minimize the variation over process, use the fastest speed grade devices so that the slow model for your speed grade will be as close as possible to the fast model.

[Altera_Forum]

Thanks Brad. I will study your responses and see where it leads me.