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Correctly using generate statements?

Altera_Forum
Honored Contributor II
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I'm trying to make a register in VHDL real quick. I have a simple DFF that I'm accessing as a component like so: 

 

ARCHITECTURE Structure OF sixteenbitreg IS Signal output : STD_LOGIC_VECTOR(15 downto 0); COMPONENT onebitreg PORT (D : IN STD_LOGIC; en : IN STD_LOGIC; clock : IN STD_LOGIC; Q : OUT STD_LOGIC ); END COMPONENT; BEGIN for i in 15 downto 0 generate reg: onebitreg PORT MAP(regIn(i),en,clock,output(i)); end generate; regOut<=output; END Structure;  

 

This doesn't compile correctly though, I don't think I'm doing it right.
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Altera_Forum
Honored Contributor II
631 Views

Generate needs a begin.

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Altera_Forum
Honored Contributor II
631 Views

I tried using loop instead of generate, didn't work

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Altera_Forum
Honored Contributor II
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jcafaro10, yeah, a loop is not correct, I read it wrong. The generate needs a begin after  

"for i in 15 downto 0 generate"
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Altera_Forum
Honored Contributor II
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so it should be: 

BEGIN 

for i in 15 downto 0 generate 

begin 

reg: onebitreg PORT MAP(regIn(i),en,clock,output(i)); 

end generate; 

regOut<=output; 

END Structure; 

 

That doesn't quite work, do I need an extra end?
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Altera_Forum
Honored Contributor II
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Here is an example of a generate: 

 

example_generate: for i in 0 to 31 generate 

begin 

 

example_inst: entity work.example(rtl) 

port map 

example_clk => clk, 

example_rst_n => rst_n, 

example_signal => output(i) 

); 

 

end generate;
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Generate needs a begin 

--- Quote End ---  

 

no, not generally. A begin is only needed, if e. g. constants are defined within the generate. 

 

The original generate example is correct except for the missing generate label. 

 

See the exact syntax definition from VHDL spec for reference 

 

--- Quote Start ---  

generate_statement ::= 

generate_label : 

generation_scheme generate 

[ { block_declarative_item } 

begin ] 

{ concurrent_statement } 

end generate [ generate_label ] ; 

 

generation_scheme ::= 

for generate_parameter_specification 

| if condition 

label ::= identifier 

--- Quote End ---  

 

Syntax elements in square backets [] are optional.
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Altera_Forum
Honored Contributor II
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Thanks I sorta figured it out

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