Connecting nodes without wires

[Altera_Forum]

One of the tutorials I found online says that nodes can be connected without wires on complicated schematics. 

 "Since our example schematic is quite simple, it is easy to draw all the wires in the circuit without producing a messy diagram. However, in larger schematics some nodes that have to be connected may be far apart, in which case it is awkward to draw wires between them. In such cases the nodes are connected by assigning labels to them, instead of drawing wires. See Help for a more detailed description."  Help is no help. I read though all 165 entries when I searched "nodes". arg.  I right clicked on a node, choose properties, name the node. Then do the same to the signal to which I want to connect, giving it the same name.  It would seem that double clicling on one of the nodes should highlight both nodes with the same name, but it doesn't.  What is the correct way to do this?

[Altera_Forum]

Geez, I thought this would be an easy one.

[Altera_Forum]

Highlight the net and hit Ctrl-F.

[Altera_Forum]

I thought it was auto-filling the Find box with the name of the node I was searching on, but it happened to be the same as the last thing I typed. So you do have to type the net name. Not ideal, but hopefully you're not doing this too much. Would be interested if anyone had a better way...

[Altera_Forum]

Rysc: 

 I have separate two nodes and I gave them the same name. Ctrl-F only finds one of them. This tells me that they aren't the same signal.  How to connect them without drawing the wires?

[Altera_Forum]

Note that this Find is not a function for finding what a net is connected to, it just Finds where that text exists in the design. Now if it finds one connection and not the other, then maybe something has changed the name of the other instance(I don't know if you have Find Whole Words Only on, but if you do, then maybe there is an extra character before or after the name, like a period or something...) Anyway, it's text isn't matching what you're looking for where another location is. Maybe delete the net, redraw and rename it, and check again. (Note that you can also go the Tools -> Netlist Viewers -> RTL viewer as another way to look at how the schemtatic is being interpreted. This probably isn't what you want, but just a suggestion...)

[Altera_Forum]

I found another tutorial online that shows how to rip signals out of busses. 

 Refer to figures 3 and 4 in this link: http://courses.ece.uiuc.edu/ece385/documents/lab_7_schematic.pdf  Similar, but not the same thing I'm trying to do.  RTL Viewer is dimmed on my pc.

[Altera_Forum]

Ok, looked at Moneyball's PLL design, and guess what. Two nets with the same name (PLL_clk), double click on one net, the other does not get highlighted. 

 http://www.alteraforum.com/forum/showthread.php?t=103  So, if you miss type the name, you won't know it just by selecting the net.

[Altera_Forum]

I think the best way to do this is to use the RTL viewer. That will show the logical connections between your blocks. Why is your RTL viewer is grayed out? Are you using web edition? 

 Otherwise you have to make sure you type in the correct name. If you make a typo on one of the nets (and assuming you don't have another net with the same name as your typo) the Quartus fitter should catch the mistake when you compile since one of the nets will not have a source.  I know this is not ideal, but these are the only options I can think of. Maybe ask Altera for an enhancement?

[Altera_Forum]

Moneyball: 

 Quartus II Version 4.2 Web Edition.  Do I have to compile before I can use the RTL viewer?

[Altera_Forum]

You don't have to compile but you need to at least do an "Analysis & Elaboration" - basically to create a netlist. 

 You should try the latest web edition - v7.1. Your version is 3yrs old.

[Altera_Forum]

My Dell Latitude only has 1.5GB free, less than 6GB total. 

 Is the schematic entry that much better in the new version? I'm an old tech and no savy HDL lingo.  My design is fairly simple:  An octal two to one mux, sixteen JK's, sixteen D's, an octal transparent latch, an eight input OR, eight two input NAND's. This is my first attempt, so I have no idea what device it will fit.  The existing discrete (asnchronous logic) design is a four channel ignition timing controller. I'm trying to update it to an eight channel system.  Pic of existing system: http://www.jandssafeguard.com/images/4chproto.jpg  The digital part of the four channel design uses 12 dips. Eight channel discrete surface mount would be a chore, so here I are.

[Altera_Forum]

Is it stated that double-clicking on a wire is supposed to highlight the other wires with the same name? I don't think this was ever supposed to happen(it does highlight the entire net it is physically connected to, but not the ones connected by name alone). In the lock_detect design, if you type Ctrl-F and search on pll_clk, it highlights both nets. 

 Note that double-clicking on a net is probably not the best way to find non-connected signals. The user would have to click on every net. Probably the best way for a generic search is to look at messages to see what logic gets removed(because of unconnected nets). The RTL viewer should work if you're looking for a specific net, but it sounds like you already know they're not connected since Ctrl-F can find one and not the other, i.e. they have different names. If you're certain they are the same, something strange is going on that needs to be debugged, rather than more tests on whether they're connected. (The schematic entry tool is probably not astoundingly better in the latest version of Quartus, but it's always a good idea to upgrade when you can.) Good luck.

[Altera_Forum]

I must add in on this discussion as this is one of the topics that I am very strongly positioned on. 

There are basically two camps of thought here.  1. The purpose of the drawing (schematic) is simply to obtain the interconnectivety of the signals by someone who knows what they are intending to connect and provide an efficeient way to pass that connectivity to a place and route tool.  2. The purpose of a drawing (schematic) is to provide a clear understanding of the interconnection of the varous sub elements within the design so that future people who refer to the drwawing can easily tell what is going on.  As I believe that all engineers really create is paperwork (electronic or otherwise) to document (capture) their design thoughts (so that others can actually execute upon it, be it another person or a computer), then I fall into# 2 above.  If you have ever had to dig in and figure out what is going on in one of those 'schematics' where all you have is big squares and stubby lines with signal names on them, you know what I am talking about.  Proper planning and thought (engineering) before you start 'dropping squares drawing lines' will provide half a chance that the structure and flow will be clarfiied by the drawing you are creating (and the lab technician will thank you 100 times over).  I say you draw the lines between the elements in you design with left to right signal flow (and place <-- reverse arrows to indicate any place where reverse signal flow occurs on the page).  In the end, you will have a well documented, easy to follow representation of your intended design (oh, and something that the P&R tool will turn into a working design).  Just my thoughts.

[Altera_Forum]

avatar: 

 When in doubt, do both. I'm the designer and the tech. Schematic entry to get the design into CPLD, then print it out and use it to fix bad boards. Oh, forgot. All the chips are inside.  So, you are saying to draw all the wires, not to rely on naming nodes for those on the other side of the page?  This goes for the common clock and presets and clears. too? Drawing area is big enough, so I'll just make room for the wires and call it good for now.

[Altera_Forum]

Yes, that is what I am saying.