Re: NIOS II Stratix board pin map

Altera_Forum · ‎03-02-2005

Greetings,

I am trying to build my own NIOS II based system that includes two (one master and one slave) modules. Is there a tcl script available for pin assignment targetted for the dev. board? I am working with EP1S10 stratix NIOS II dev. board. A simple hello_world program wouldn't run after copying the pin assignments and having all the components as are present in the reference "standard" design. Debug results in "undocumented error code -1"!

Thanks in advance.

Ajit

Altera_Forum · ‎03-02-2005

First, I would make sure that you copy the whole section from the csf to your new csf.

I believe that we list all pins in the csf's now. But depending on the version you're copying from, they may or may not all be there. what version of Nios (I or II) are you getting the design from?

Altera_Forum · ‎03-03-2005

Thanks Kerri, for a prompt reply.

I am working with NIOS II, with quartus II 4.2 SP1 and NIOSII IDE 1.1. There is no csf file existing in the "standard" project directory. I double-checked the pin-map I have created using my own tcl script with that of the standard design. Just for the heck of it, I have kept all the modules and their base addresses identical to that of the standard design. However, I am not using the bdf file for top level entity generation, and including SoPC builder-generated vhdl file in the quartus project.

Am I missing a crucial pin-out? I have simulated the design and a simple program in Modelsim and it works fine. When I try to debug, the debugger doesnot show me the source statement @ which the processor is presently halted, but goes in a loop and loses control after a while.

Thanks and regards,

Ajit

Altera_Forum · ‎03-03-2005

To help with debug can you ensure that the SysID peripheral is in your system (make sure your hardware and software are in sync). Also I think Kerri meant "qsf" file which you will see a lot of pin assignments. I would just copy the ones you really need and leave the rest unassigned. Another thing is, you should make sure that all unused I/O are tri-stated (it's in the Device&Pin settings). That was you don't have stray I/O being assigned where you don't want them to be (like a pin connected directly to ground for example).

If you have LEDs available and routed just like in the standard design, I recommend that you use "Hello-led" to see if the design is alive at least (that way you have minimal reliance on the JTAG uart). If that looks fine then work from there.

Good-luck