How to gnerate a FIFO with these parameters

[Altera_Forum]

I want to generate a 32x5 fifo for my design with the following parameters. I have the older version of this FIFO but is actually gnerated from altdpram megafunction (which I can percieve),but I have also found out that altdpram is no longer supported instead altsyncram is supported ,but I cannot afford changing the parameters otherwise I have to change the whole design 

defparam fifo32x5.LPM_WIDTH = 5;  defparam fifo32x5.LPM_WIDTHAD = 5 ;  defparam fifo32x5.INDATA_REG = "INCLOCK" ;  defparam fifo32x5.WRADDRESS_REG = "INCLOCK" ;  defparam fifo32x5.WRCONTROL_REG = "INCLOCK" ;  defparam fifo32x5.RDADDRESS_REG = "OUTCLOCK" ;  defparam fifo32x5.RDCONTROL_REG = "OUTCLOCK" ;  defparam fifo32x5.OUTDATA_REG = "UNREGISTERED" ;  defparam fifo32x5.INDATA_ACLR = "OFF" ;  defparam fifo32x5.WRADDRESS_ACLR = "OFF" ;  defparam fifo32x5.WRCONTROL_ACLR = "OFF" ;  defparam fifo32x5.RDADDRESS_ACLR = "OFF" ;  defparam fifo32x5.RDCONTROL_ACLR = "OFF" ;  defparam fifo32x5.OUTDATA_ACLR = "OFF" ;  defparam fifo32x5.LPM_HINT = "USE_EAB=ON" ; However while compiling this module in Precision( a mentor tool ) followed by pnr in Quartus II ,Quartus II issues a warning Warning: Assertion warning: altdpram does not support Stratix II device family -- attempting best-case memory conversions, but power-up states and read during write behavior will be different for Stratix II devices  Plz help..

[Altera_Forum]

You have to upgrade the old altdpram megafunction or live with the warning. 

 If Precision is inferring altdpram when a Cyclone or Stratix device family is selected, then Precision has a problem. If you are instantiating the megafunction yourself, then of course Precision is not at fault. If you are using a FIFO megafunction that is in turn using altdpram, then make sure you have the correct device family selected for your FIFO megafunction.  From on-line help:    --- Quote Start ---  altdpram Megafunction   --------------------------------------------------------------------------------  Parameterized dual-port RAM megafunction. this megafunction is provided only for backward compatibility in cyclone, cyclone ii, hardcopy stratix, stratix, and stratix gx designs; instead, altera recommends using the altsyncram megafunction. The altdpram function uses Embedded System Blocks (ESB) in APEX 20K and APEX II devices, Embedded Array Blocks (EAB) in ACEX 1K and FLEX 10KE devices, or DFFE primitives or latch arrays in FLEX 6000, MAX 3000, and MAX 7000 devices, or if the USE_EAB parameter is set to "OFF". altera strongly recommends using synchronous rather than asynchronous ram functions. You can use the altdpram function to access ACEX 1K, APEX 20K, APEX II, and FLEX 10KE dual-port RAM hardware features that are not available in lpm_ram_dp, such as asynchronous clear of registers.  --- Quote End ---  

[Altera_Forum]

I think I was not a bit clear in this case I am using A code in which I am instansiating a FIFO which is generated using altdpram,Now when I run Precision on it fllowed by Quartus place and route with the tcl file gnerated by precision ,Quartus gives a warning  

Warning: Assertion warning: altdpram does not support Stratix II device family -- attempting best-case memory conversions, but power-up states and read during write behavior will be different for Stratix II devices And it takes   Info: Implemented 17 input pins Info: Implemented 5 output pins  Info: Implemented 5 RAM segments  Now if I run the same design on Quartus II(integerated synthesis and place and route),it gives no such warning but instead gives the warning Warning:Design contains 17 input pins that do not derive logic. Info: Implemented 17 input pins  Info: Implemented 5 output pins But no RAM segments.  What could be the possible reason?