Altera Devices with built-in Clock ???

[Altera_Forum]

Hi All, 

 Can someone tell me if any Altera devices have a built-in Clock?  I currently use the max7000 series (7064/7128) chips for small projects such as lighting chasers and low-speed control (in the order of KHz), but i'm still using an external (555 or cmos 4040) clock source to clock my devices.  I'd like to eliminate external chips, and simply have a single Altera device on small PCB for my applications.  I prefer PLCC socket devices, but will move to solder type if i really have to ;-)  Thanx in advance, Marty

[Altera_Forum]

The December 2006 MAX II handbook (there might be a newer one) says this in the User Flash Memory Block section: 

   --- Quote Start ---  Internal Oscillator  As shown in Figure 2–15, the dedicated circuitry within the UFM block contains an oscillator. The dedicated circuitry uses this internally for its read and program operations. This oscillator's divide by 4 output can drive out of the UFM block as a logic interface clock source or for general-purpose logic clocking. The typical OSC output signal frequency ranges from 3.3 to 5.5 MHz, and its exact frequency of operation is not programmable.  --- Quote End ---  

[Altera_Forum]

Hi,  

 This might also help: http://www.altera.com/literature/hb/max2/max2_mii51010.pdf  One interesting text at page 9-8    --- Quote Start ---  Instantiating the Oscillator without the UFM You can use the IO/MAX II oscillator megafunction selection in the MegaWizard® Plug-In Manager to instantiate the UFM oscillator if you intend to use this signal without using the UFM memory block. Figure 9–4 shows the altufm_osc megafunction instantiation in the Quartus II software.  --- Quote End ---    Looks like this oscillator can be used, where the timing is not critical and this much (3.3-5.5 MHz) tolerance is acceptable, probably from device-to-device. I haven't used this feature so far, but if someone here is using this feature, then he/she can solidify this concept and its usability. If the variation in output frequency from device-to-device is very little, then this is really a nice feature, especially for low frequency applications.  -BD

[Altera_Forum]

Thanx for the info guys, i'll look into the internal osc asap. 

 I guess i'd simply feed this 3-5mhz signal into a divide-by-n counter, to give me a clock in the order of 100'sHz to a few KHz. My applications are usually nothing that relies on critical timing, such as light chasers or logic control of other gear. I'm sure if the freq differs between devices it probably won't affect my projects too much, at least nothing i'd probably notice ;-)  I could always tweak the clock divider for each chip if i was having probs ;-)  Thanx again, this is a step forward.......so far, Marty.

[Altera_Forum]

--- Quote Start ---  I guess i'd simply feed this 3-5mhz signal into a divide-by-n counter, to give me a clock in the order of 100'sHz to a few KHz.  --- Quote End ---     Even if you have lots of positive clock setup slack at these low frequencies, you have to be careful about clock hold at any frequency, especially if you will have any paths crossing to or from the divided-down clock domain. If you have all your logic on the divided-down clock and make it global, you'll probably be OK without having to do anything extra. See my posts at http://www.alteraforum.com/forum/showthread.php?t=754 for more information.

[Altera_Forum]

Hi Brad, thanx for the extra info. 

 So, are you saying that after i've 'divided down' the clock to an appropriate amount, i should send it OUT a pin, and feed it back into the master Clock Pin to be safe/stable?  Thanx again, Marty.

[Altera_Forum]

You do not need to send the clock out a pin and back in a pin (unless that is the only way to use a global in MAX II--I didn't check that). Going out of the device and back in won't help with any of the timing issues. 

 Most of the timing issues with a global divided-down clock are for paths that cross to and from the divided-down domain. As I said before, you'll probably be OK if you have all your logic on the divided-down clock and make it global. If you will have logic on more than one clock with synchronous paths between the domains, then beware of the caveats I posted in the other thread.

[Altera_Forum]

MAX 7K families had a dedicated input pin for global clocks. MAX II does not have this restriction -- its much more flexible in architecture and features. Any internal signal can route internally to a global clock signal. It behaves like the FPGA families in these regards. It also have 4 global signal lines to use.