connect 2 PLLs in cyclone II

[Altera_Forum]

Hi all! 

I create a project in cycloneII 35. I must use 2 PLLs from 1 external clock. So, I must connect them. But when I do this, there're many problems. For examples, when compiling there's error: "can't fit fan-out of node clk_dram (name of one PLL) into single clock region." Who knows how to solve this problem to use 2 PLLs in my project. Please tell me, thanks!:confused:

[Altera_Forum]

Hello, 

 Unfortunately you can't do that. As you can see in the page 7-26 and 7-27 of the cyclone II handbook, each PLL can be drived only by its dedicated input ports. Then there is no way to connect one source with two PLLs.  Thanks,

[Altera_Forum]

I've tried to apply many ways. But, in the end I failed. Probadly, I can't do this. It means that I must use one separated input clock for each PLL. Is there any solution for this problem? Please show me! Thanks for Bee's helping!

[Altera_Forum]

As said, Cyclone II doesn't support chaining of PLLs as you can do e. g. with Cyclone III. 

For this reason, I usually routed the main clock input "all around" the FPGA in Cyclone II designs. If you need a PLL function without strict timing requirements, you can probably output it to a pin next a dedicated clock input and route it through pins. A routing delay could be compensated by PLL phase shift.

[Altera_Forum]

Maybe you can use two pins and use clock skew in order to compensate layout based delays.