"end of initialization" reset

[Altera_Forum]

Hi everybody, 

 Are there internal power-up reset or "end of initialization" reset signals that can be read to check for start-up reset condition in cyclone FPGA's?  Whitebird

[Altera_Forum]

Would the optional INIT_DONE output give you what you need? 

 Every internal register will be cleared at power up. You could have a register continuously clock in a high data input. When the register output goes high, you will know that the power-up reset phase has ended.

[Altera_Forum]

Thank you for fast answer Brad. 

 The problem with INIT_DONE is that I don't know id it can be read internally    --- Quote Start ---  Every internal register will be cleared at power up  --- Quote End ---    OK, but it seems not to be the case for state machines.  I have a state machine like that (VHDL):  type state_machine is(P1,P2,P3); signal state,statef:state_machine;  But after end of initialization the first state is P2 and not P1! I want it to be P1.  Don't know why it goes to P1.  The state will be P1 only by the help of an external reset pin.  Whitebird

[Altera_Forum]

--- Quote Start ---  The problem with INIT_DONE is that I don't know id it can be read internally  --- Quote End ---    Why do you need a signal to know internal to an FPGA that that same FPGA has completed initialization? When internal logic starts operating (as it has to do in order to look at an internal status signal for end of initialization), you know initialization has ended.  There is no guarantee that every register in the device will exit the power-up reset condition at the same clock cycle. If you are wanting to create an internal reset signal that will make sure everything starts up on the same clock cycle (a good design practice), you can use my suggestion of a register clocking in a high as soon as possible. That register output can be the starting point for internal reset signals synchronized to the various clock domains.      --- Quote Start ---  OK, but it [every register being cleared at power up] seems not to be the case for state machines.  I have a state machine like that (VHDL):  type state_machine is(P1,P2,P3); signal state,statef:state_machine;  But after end of initialization the first state is P2 and not P1! I want it to be P1.  Don't know why it goes to P1.  The state will be P1 only by the help of an external reset pin.  --- Quote End ---     If any of your states is encoded with all state bits low, that will be the state at power-up reset unless you override it with a reset signal to force a different initial state. If you want P1 to be the reset state at power up without asserting the reset signal and also to be the reset state when the reset signal is asserted later, then the P1 state code must have all bits low.  This can be confusing if synthesis inserts inversions to make an internal register appear to power up high. I think that for all devices all internal registers power up low; any apparent high is accomplished with inverters. Some devices let you force registers to power up high, but I think that makes only I/O cell registers power up high (because there is no inverter available in the I/O cell to make an actually low register act like a high register).

[Altera_Forum]

Excerpt from my post at http://www.alteraforum.com/forum/showthread.php?p=4560#post4560: 

 If you are using Quartus integrated synthesis, then in the Quartus handbook see Volume 1, Section III, Chapter 8. Read the "State Machine Processing" section and the following sections. The handbook tells you how you can optionally encode your states manually (there's also a VHDL template in the text editor for this).  For automatic one-hot encoding (and I'm guessing for other encodings that are not user-specified), this section of the handbook says, "Quartus II integrated synthesis encodes the initial state with all zeros for the state machine power-up because all device registers power up to a low value." I didn't know whether "the initial state" means the first state listed in the type definition or if synthesis determines it from a reset signal in the state machine to make the power-up reset state match the one controlled by the reset signal. I did an experiment and found that the state forced by an asynchronous reset signal (I didn't try a synchronous reset signal) is always the one that gets encoded with all state bits low when "State Machine Processing" is set to "Auto". The all-bits-low state isn't necessarily the first one listed in the type definition.  Check the Analysis & Synthesis report for the actual state encoding. It is shown in messages and in a table.

[Altera_Forum]

Thanks a lot for all this precise information Brad. 

 Whitebird