MegaCore FFT in Quartus

[Altera_Forum]

I'm working on using the MegaFunction FFT in Quartus on an Altera DE2 board, but have had issues finding documentation of the inputs/outputs to the function. I've scoured these forums for a while, but it seems most people are using the DSP builder for simulations.  

 The goal is to be able to output the FFT of an audio signal from the board's line in. I have generated the function block (Streaming) with all the required values , but I'm rather confused about the inputs and outputs to the function.   Am I supposed to divide the 50 Mhz clock signal for the sink_eop, sink_sop, source_sop, and source_eop? Can I just set reset, sink_ready, sink_valid, source_valid, clk_ena as high and inverse as low? What other inputs other than sink_real and sink_imag are needed?  It would be great if someone could provide a for a working example. If privacy is an issue, my email is [angryconsumerism at gmail ]. Thanks!

[Altera_Forum]

Hi, angryconsumerism, 

 A testbench is automatically generated when you instantiate a FFT core (in DSP Builder or Quartus). Perhaps taking a look at the generated test bench might give you a better idea...  I will try to de-cipher it for you a bit: - Your 50 MHz clock would go into the clock input port and nothing else... - sink_sop and sink_eop: these are start and end of packets signals for your inputs... you would have to code a FSM that generates these signals for you... - sink_valid -> DO NOT just set this to high... the signal is used to tell FFT whether inputs are valid or not... you might want to check with sink_ready (an output signal)... - source_ready -> you would have to assert/de-assert this signal, to let the FFT know whether the downstream modules are ready for outputs or not... - source_eop, source_sop, source_valid: these are output signals that you do not have to set yourself...  Of course it depends on what architecture you are trying to use... if you tell me more about your FFT, I might be able to help you more....  Good luck!

[Altera_Forum]

Alright, I spent a lot more time looking at it, and I think I know how the states work; however, I'm not sure how it works with the timing of the input samples. I'm inputting the line in for the real part and setting the imag input as 0, which is sampling at 8 Khz. Does the input frequency affect anything at all? 

 Right now, the FFT setting is taking 4096 points, but I'm not particularly sure how long a packet should be.  Any help would be great. Thanks!

[Altera_Forum]

If you have set the points to be 4096, you must have one packet with 4096 valid data. The valid data means, when the sink_ready and Sink_valid are both high, we call it a valid data. And the valid data between SOP and EOP signal should be 4096.

[Altera_Forum]

I'm stuck. I attached the source and would appreciate if anyone could comment on a few issues: 

 1. I get a "can't place pins" error on the audio_in and audio_out, which results in a "can't fit design in device" error. I double-checked the locations in the assignments editor, and everything is tied to the right pins (AUD_DACDAT, AUD_ADCDAT). I also changed the Pin I/O settings so nCEO is set as normal I/O instead of programming pin. I'm using Quartus 7.1 Build 178 so I don't have the Quartus 6.0 error.  2. I was not able to set sourcevalid successfully. If you look at the source, I commented out a line which would set the sourcevalid since I was getting a "multiple constants" error. The only other time that sourcevalid is used is in the port map. Am I doing something wrong or is there a workaround?  3. Since I can't test it, I'm not 100% sure if the thing works conceptually.  Thanks!

[Altera_Forum]

--- Quote Start ---  I get a "can't place pins" error on the audio_in and audio_out  --- Quote End ---   Cause the audio codec has a serial interface, you can't place a parallel bus for input respectively output. You need to use a serial transceiver and transmitter as in the DE2 demonstration projects.  Although I don't know the FFT core from own applications, I see that source_valid is an output from the core. Thus it can't be set without causing an error. But users with detailed knowledge of FFT core may give suggestions related to your code.

[Altera_Forum]

That makes sense. It should work with just an audio input right? I didn't assign an output and it still gives me the errors. 

 Ultimately, I'm trying to display to VGA - Does anyone know how the output std_logic_vector/array relate with the waveform? Do all 24 bits correspond to the magnitude? Unfortunately, I can't simulate it since I don't have the right version of MatLab to use the DSP Builder. I'm working to use an external simulation with the IP cmp file, but I haven't been successful yet.  I realized I put in some Java/C++ comments so here's an updated version.

[Altera_Forum]

Hi, I would like to use the FFT MegaCore IP. After generating the code, I want to pass the inputs and fet the outputs. I want to write a top level file.v which able to give the inputs and get the outputs from the FFT generated file. My top level file.v looks like the test bench file. I am giving 64 points but there is NO outputs. 

 Please, anyone can help me.

[Altera_Forum]

hi everyone, 

 I am new to fft megafunction. I make all instructions on the fft megafunction user guide . I have an 16k point fft at least.  but after doing this how can use this ? is there any one can help me?  I looked for an example but I cant find. I have a video stream and I should make its fft and then take its phase and store it. this is my goal.  but I really confused about using this.  shoul I take the fft.v file and take it in my video project ?  please help me :(

[Altera_Forum]

Hi，are you still working with the FFT megacore? The same problem puzzled me now.I just created a fft ip core by Quartus II.But I don't know how to use it.  

Do i need to wirte a state machine to control the sink_sop,sink_eop,sink_valid? For example I want to analyse the signal sin(x) (0:1:1024) by FFT. I have got the 1024 pionts by matlab and saved the datas by file. How to set up the input datas? 18bits and one by one or together?

[Altera_Forum]

Hi all, 

 I am using FFT megafunction too for my final year project. The problem i had face is i can't get the output of last FFT block since it's size(eg 7 points) is not same with the previous FFT blocks size (eg 8 points). I had follow the instruction Dynamically changing the FFT Size in the manual but still can't get the output of the last FFT block. Anyone face this problem before or any idea to solve it?   Here my waveform attached. I had refer to the Figure 3-8 (Dynamically Changing the FFT Size) of FFT megafunction.

[Altera_Forum]

Hi all, 

 I want the block diagram or architecture of the FFT megacore function, so that I can understand it better and know,how the DSP blocks are utilized . Can anyone help me with this? Does anyone know, where it can be found??    regards, Renif

[Altera_Forum]

Hi all 

i am using same FFT core for estimating Power harmonics. For finite state machine how i can decide for control signals. Kindly help. Regards

[Altera_Forum]

Hi all 

i am using same FFT core for estimating Power harmonics. For finite state machine how i can decide for control signals. help is needed. Regards

[Altera_Forum]

Hi ! 

 I am new to megacore I generated the FFT core in vhdl. But I couldnt to run the stimulation in modelsim. I attached the tb_fft.vhd fft.vhd and fft.vho file to the project in modelsim.Should I do more? please help.

[Altera_Forum]

Why do people continue to post new questions to this 7 year old thread?? 

 ferdi - Start a new thread - you'll get much more attention that way.