How to use LVDS?

[Altera_Forum]

in datasheet,i find maybe it isn't similar to use LVDS in Cyclone1,cyclone2,and cyclone3, 

so what can i do if i want to use LVDS? 1,does it need resistor? 2,how many wire i need ? in my opinion there is two way to do this the one is two wire and use CDR, and the other is four wire use two to send data ,and two as clock reference. can you tell me the trues? thank u

[Altera_Forum]

and in xilinx there is no need to use resistor?

[Altera_Forum]

Hello stephenzhou. Yes, you should use external resistors in Altera and Xilinx.  

I'm going to use LVDS too. And I have some questions. I have a devboard from Atmel with LVDS outputs and I want connect it with my Cyclone board. In datasheet I have read, that Atmel board has 100 Ohm termination resistors. So I can connect it directly to Cyclone pins. But distance between resistors and Cyclone device is very long( much longer, than recomend Altera). Will be it work? Can it damage chips?

[Altera_Forum]

in my opinion,it will not damage chips. 

and in datasheet the long u use the speed will go slowly. U can try it. good luck! and i want to ask u how many wire do you use ?

[Altera_Forum]

I will try :-) Now I use 18 wires (8 bit data and 2 wires for clock). But in future I'm going to use 16 bit data bus. 

Note: CycloneIII has dedicated output buffers for LVDS so no external resistors required.

[Altera_Forum]

u didn't use encoder for CDR? 

and it just use 16 wires for 8bit!  and good luck!

[Altera_Forum]

I use 16 wires, because Atmel DSP board transmit 8 bit per clock at very high speed. You can serialize your data and use only 4 wires.

[Altera_Forum]

thank u NICK. 

What u said 4 wires ,just 1wire for data 1 wire for different data ,1wire for clock 1wire for clock?

[Altera_Forum]

Yes. Differential pair for data and differential pair for clock. I successfully used this circuit. Also you can try to use 3-wire circuit, as you wrote in first post.

[Altera_Forum]

3-wire? 

may be 2 wire and data with clock in CDR.

[Altera_Forum]

Yes, you are right.

[Altera_Forum]

Thank u Nick it's very kind of u . 

and can you tell me about the follow things of your LVDS? i wish you will succes in your project!

[Altera_Forum]

Thank you! I wish you success too!

[Altera_Forum]

I think there's some confusion on the terms being used here... 

 LVDS is a differential I/O standard that specifies voltage levels. There is no specific form of clocking implied by using an LVDS I/O standard. Some Altera devices have native support for LVDS, while some devices require external components (resistors) to get the voltage levels right.  CDR is Clock-Data Recovery. This is a method of extracting (recovering) a clock from a data stream. At higher speeds (generally above 1.25 Gbps), the problems with controlling the relationship between a clock signal and a data signal are great enough that you really need to get the clock from the data transitions.  The scheme where you send the clock along with the data as a separate signal is often called "Clock Forwarding." Interfaces like this (SPI4.2, for example) use one or more data lines and a separate clock. For higher speeds or longer traces or more connectors, you often want to have a way to dynamically adjust the relationship between the forwarded clock and the data lines. Some of the Altera devices have the capability to do this with DPA (Dynamic Phase Alignment).  Going back to your original question, I think you were asking what Cyclone I, II, and III support relative to these terms...  Cyclone I and Cyclone II support LVDS, but only with external resisitors. Cyclone III added a true LVDS output buffer, so you don't need to use external resisitors on the transmitters. However, the resistor required on the receive side is still external for Cyclone III. If you want to use LVDS to communicate with a Cyclone device, you'll probably have to use some sort of clock-forwarding scheme.  CDR is only available in Altera's "GX" devices. There are generally fewer of these transciever channels, though they are able to run much faster than any of the more traditional I/Os (over 6 Gbps). In general, "CDR" and "Cyclone" are two terms that don't go together.  DPA is available in the newer Stratix devices (II and III).  And here's one more I'm throwing in just because I see it misused all the time and I'm on a roll here...  SERDES: This is a circuit that can take fast serial data and convert it to parallel (or vice versa). Having a SERDES does NOT imply that you have CDR. All the Stratix devices have a dedicated SERDES in some of the I/O cells. Cyclone devices use the regular logic to serialize and deserialize the I/O.  I hope that helps. I'm still not sure I answered your question, mostly because I'm not exactly sure what you were asking, but I tried.

[Altera_Forum]

I like thatNick noted that Cyclone III has dedicated LVDS input and output buffers now. This is a big improvement.  

 Cyclone I, II, III only support source synchronous LVDS -- no dedicated clock recovery circuitry. You need Stratix IIGX for CDR. This is why Nick is using clock + data for his LVDS interface with Cyclone families.    you could potentially run a very slow data rate and do oversampling, i.e. you have 100 Mbps data rate, but you run the PLL / LVDS interface on Cyclone I, II, III at 800 Mbps and get 8 sets of bit data for each 1 bit of 100 Mbps you need. You would need some period to quickly train which bit location is the best to take, some voting algorithms exist for this.

[Altera_Forum]

Hi All , 

 I remember that Altera had a ASI / SDI development board in 2004 There were two versions of boards , One of them was a low cost solution , and another one was a high-en solution  The device on the low cost ASI / SDI development board was EP1C6T144C6 As there was no dedicated CDR circuitry in Cyclone I FPGA Altera had a reference design on CDR algorithm in Cyclone I FPGA  That was a reference design doing CDR for a 270Mbps LVDS signal (Which is a kind of over-sampling actually) Say Data Rate = 270Mbps Input Crystal Freq = 27MHz  Use PLL to generate a clock of 337.5MHz , we call it SCLK Then use the PLL to generate another clock of 337.5MHz with 90 degrees phase shift we call this clock signal sclk90  Invert this 2 clock signals , SCLK (0 degree phase shift) SCLK90 (90 degree phase shift) ISCLK (180 degree phase shift) ISCLK90 (270 degree phase shift) Then we sample the input data with these 4 clock signals And finally resynchronize the data to 27MHz , the output is a 10 bit data Virtually this is a 5 times sampling (270 x 5 / 4 = 337.5)  Is Steven talking about this kind of CDR in Low Cost FPGA ?

[Altera_Forum]

Just to be really nit-picky here, the UART-like ASI/SDI oversampling solution is not a CDR system. It does a fine job at recovering the data, but there is no clock recovered. By the time the receiver gets the data, it is running along at the local clock frequency and there is no way to recover a clock at the receiver that has a 0 ppm difference from the transmit clock.

[Altera_Forum]

Hi Bland Guy , 

Thanks so much for your answer It seems I have misunderstood CDR ...

[Altera_Forum]

Hello stephenzhou, 

The cyclone device doesn't have CDR function, neither does stratix 1 and 2 on the LVDS port, so you should use it with reference clock. You don't need clock for each data line, and may be able to send 2bits data with one referece clock. I depends, however, on the frequency and board skew. Thanks,

[Altera_Forum]

thanks very much.

[Altera_Forum]

How long are your runs? It is important to make sure that the lengths of all the runs are close, otherwise signals will arrive at the destination at different times causing setup/hold problems.