VHDL code for Right Shift register

[Altera_Forum]

Hello All.. 

 I have problem in my code. I have created code for 8 bit shift register right..  ie my input is 11001011 then in  1st clock :- output should be :- 01100101 2nd clock :- output should be :- 00110010 3rd clock :- output should be :- 00011001 4th clock :- output should be :- 00001100 5th clock :- output should be :- 00000110 6th clock :- output should be :- 00000001 7th clock :- output should be :- 00000000(Ie at the end of clock 8, it should be 0h)  Please correct my code :-  library ieee; use ieee.std_logic_1164.all;   entity shift is  port(C, SI : in std_logic;  SO : out std_logic); end shift; architecture archi of shift is  signal tmp: std_logic_vector(7 downto 0);  begin  process (C)  begin  if (C'event and C='1') then  for i in 0 to 6 loop  tmp(i+1) = tmp(i);  end loop;  tmp(0) = SI;  end if;  end process;  SO = tmp(7); end archi;  Thanks a lot

[Altera_Forum]

What did you write so far and what do you need? I don't think you'll get a ready made answer here.

[Altera_Forum]

--- Quote Start ---  What did you write so far and what do you need? I don't think you'll get a ready made answer here.  --- Quote End ---    well..actually..we don't know where to start and how the program works. Our instructor or demonstrator told us to copy the vhdl code from any web. And so far, we got nothing..all the coding we found, gave a lot of errors and we don't know how to fix them. Also, we do not know whether the coding we got from the web is the vhdl code for 5bit left-to-right shift register..:confused::(

[Altera_Forum]

Your instructor gave you some rather weird instructions... copying something from the web has several problems. First you can't be sure it's correct, second sometimes the context is missing so you don't know if you can directly use it in your project, and mostly you don't understand what it is doing. You will same a lot of time just doing it yourself, especially if you are supposed to learn VHDL at the same time. 

Before doing the shift register itself you need to define the context. What are your component's inputs and outputs? Define an entity with the input and output ports, and then work on the operation itself. In VHDL the sll (shift left logical) and srl (shift right logical) can be used to perform shift operations.

[Altera_Forum]

--- Quote Start ---  Your instructor gave you some rather weird instructions... copying something from the web has several problems. First you can't be sure it's correct, second sometimes the context is missing so you don't know if you can directly use it in your project, and mostly you don't understand what it is doing. You will same a lot of time just doing it yourself, especially if you are supposed to learn VHDL at the same time. Before doing the shift register itself you need to define the context. What are your component's inputs and outputs? Define an entity with the input and output ports, and then work on the operation itself. In VHDL the sll (shift left logical) and srl (shift right logical) can be used to perform shift operations.  --- Quote End ---    hahaha.....tell me about it...the instructor just teach us the basic of vhdl code only...which is totally basic thing only..like how the body of programming of vhdl code should look like...all the define things like where is the input and the output is never been told before...when we copied one of the vhdl code from the web..we got some errors and try to ask her about those...well, she did taught to us about that code(more like explaining how the code worked and how to re-correct the errors)..and of course we don't understand a thing about the code...because we never learned about the vhdl code deeply...anyway, sorry for bothering as we already presented our project...if we had other kind of projects regarding this vhdl code...we will ask again..thank you!:D

[Altera_Forum]

--- Quote Start ---  hahaha.....tell me about it...the instructor just teach us the basic of vhdl code only...which is totally basic thing only..like how the body of programming of vhdl code should look like...all the define things like where is the input and the output is never been told before...when we copied one of the vhdl code from the web..we got some errors and try to ask her about those...well, she did taught to us about that code(more like explaining how the code worked and how to re-correct the errors)..and of course we don't understand a thing about the code...because we never learned about the vhdl code deeply...anyway, sorry for bothering as we already presented our project...if we had other kind of projects regarding this vhdl code...we will ask again..thank you!:D  --- Quote End ---    It's very simple really.   The code for a left to right shift register is....  shift_reg(3 downto 0) <= shift_reg(4 downto 1);  ..ie take the bits in (4..1) and assign them to (3..0). If you want to set the bits to '0' as it shifts you can add shift_reg(4) <= '0';   A right to left shift reg is... shift_reg(4 downto 1) <= shift_reg(3 downto 0); shift_reg(0) <= '0';  Draw this out on a bit of paper and you'll see how simple it is.  You need to have some structure round this to initialise the register (with a reset statement probably) and to control when the shift happens (on a clock edge probably). I'll leave that up to you.  Nial    If you look at simple code examples on the web you'll see there's

[Altera_Forum]

And I suggest that you go to your university's library and borrow a good VHDL book. It will save you a lot of time on the long run.