Pinout compatibility across EP3Cxx devices

[Altera_Forum]

We are in design with an EP3C40. We chose the F484 package in order to have upward compatibility to place larger FPGA devices on our circuit board if our design requires greater FPGA resources. I notice that the larger devices (EP3C55, EP3C80, EP3C120) are listed as having fewer user I/O pins. How can we best determine which pins in the EP3C40 to use, so that we can utilize the larger FPGAs (if necessary) on the board layout we are now doing? Is there anything else we should know, or be considering, along these lines? Thanks very much...

[Altera_Forum]

The most convenient way ist to define the intended migration devices additionally in device selection and let Quartus check the design compatibilty.

[Altera_Forum]

Thanks very much for the quick reply, I really appreciate it. Unfortunately, I don't have access to the Quartus system right at the moment (someone else is doing the detailed design, and he's not available today), is there something in the literature that might list them, or anything similar? I've got a pinlist file from the 3C40 design...just wanting to see how many of those I/O pins that we've used might need to be reassigned (to pins which are common to all the devices), layout is approaching very fast. Hopefully just changing them will do it? I now wonder, though, if the bigger devices have fewer I/O pins available, those pins must have been used for something; will they need to be connected (e.g., power/gnd or something) for the bigger device? Presumably that won't make the smaller device unusable? What else am I missing? Sorry to be such a newbie on this...

[Altera_Forum]

the larger density devices in the same package have more vcc/gnd pins. this thread is helpful: 

 http://www.alteraforum.com/forum/showthread.php?t=106

[Altera_Forum]

Thanks....

[Altera_Forum]

--- Quote Start ---  the larger density devices in the same package have more vcc/gnd pins.  --- Quote End ---  Basically. Unfortunately, there are some irregularities particularly with pin mapping of Cyclone III devices. Thus it's strongly recommended to check the final assignment with Quartus before producing the PCB.  Apart from having Quartus to check the pinning, I usually combine the Excel pinouts of the intended migration devices into one spreadsheet.

[Altera_Forum]

Thanks very much for all the replies. I think I understand things a lot better now; for the possible benefit of others who may stumble upon this thread, I'll summarize a few of my additional detailed findings in this case. 

 It seems that indeed having Quartus II take care of things is highly preferred, given the complexity. In general, it is clear that, as I'd guessed, the more dense devices have more VCCINT and GND and thereby less IO, but no real details or clear explanatory pronouncements seem to be available. So (in the temporary lack of Quartus II availability) I found pinout spreadsheets on altera.com (http://altera.com/), and compared the 3C40 and 3C120 (since it's kind of a pain, I only did one, the biggest one, as I figured it would likely have the most extreme differences). I now understand more about what the various folks have been saying, and it is decidedly a bit crazier (irregularities) than I had anticipated.   Comparing the pin name / function as listed, there are 78 that are different. As expected, there are many (63) that are IO on the 3C40 and either VCCINT or GND on the 3C120. Interestingly, it appears that there are 15 IO on the 3C120 that are GND (7) and VCCIOn (8, one from each bank) on the 3C40 -- who knows why things were done this way? Anyway, this jives with the different numbers of IOs quoted for the two parts (331 - 283 = 63 - 15). It seems like it might be a good idea for Altera to somewhere list the number of IO pins that are common between the various devices in a given package, since it's not necessarily straightforward, and appears to be less than one might anticipate from looking at their tables -- in this case, there would only be 268 (still more than enough for us, but...).   I then looked at those 78 pins in our .pin file. Of course, those (15) that are VCCIOn and GND in our design should be fine; if we populate with the more dense part, those IOs can just be unused. But it appears that the other 63 (IO on the 3C40) were indeed appropriately assigned as GND or VCCINT in our design (now I understand the innards of that much better, just from looking at the .pin file alone it was hard to guess which were which), matching the more dense part, so it looks like that will work fine as well.   I don't know for sure what the detailed situation is with the other parts (3C55, 3C80), but I can assume that it will be similar (and maybe not even necessarily "linear" in terms of being intermediate between the other two) -- I suppose I could check, but I'm guessing that, as long as we specified those parts in the Migration Device list, Quartus II will make it work similarly (albeit somewhat hidden behind the scenes), as it appears to have done for the 3C120. Given the craziness, it does seem that Quartus II is the only rational way to handle this in general, once one understands and trusts the tool (and foresees enough / remembers to enter the migration devices, which our designer wasn't sure he had done); it can be done otherwise, with some hassle, but...    Now, maybe for some future date, it might be interesting to know about any similar potential migration to the LS parts, for Design Security -- on a quick look, it seems that lots of clock pins have been moved, but this isn't on my hot path right at the moment.   Thanks again for the help!