Clock characteristics for MAX II devices

[Altera_Forum]

Hi Folks, 

 In my board, I want to give 66MHz clock to MAXII CPLD (EPM1270). While referring CPLD datasheet, I can't able to found any recommended clock characteristics (frequency tolerance in ppm or jitter requirements) except its frequency.  Can I get any documents(application notes) recommending clock characteristics for MAX II CPLDs or any other suggestions.  Regards, VJN

[Altera_Forum]

I guess it primarily depends on what the requirements are on the stability of your outputs. 

 So longs as the jitter is not utterly terrible and your device meets your 66MHz timing requirements then you shouldn't have any internal timings problems

[Altera_Forum]

Jitter is a relevant parameter for FPGA that are driving a PLL from the clock. MAX II has no PLL, so maximum frequency, minimum pulsewidth and rise/fall times are the only parameters of interest.