SSRAM (IS61LPS25636A)) on Cyclone III starter board

[Altera_Forum]

I am trying to read a bunch of data from SSRAM (IS61LPS25636A)) on Cyclone III, which is 256k*32 bit in size. However, from the board manual, there are 32 data bits, 21 address bit (should be 18 bits for 256k), Does anybody know this problem? what are the additional three pins?

[Altera_Forum]

I downloaded your project. I had to recreate another one and import your files in it because your project made my Quartus 9.0 crash. 

As I told you in a previous message, you don't have any clock going out of pin A2. I created an extra output pin called ssramclk, assigned it to pin A2, and connected it to the signal ssramclk_test. It seems to work fine now.

[Altera_Forum]

Thanks. Can you upload your project on http://demo.ovh.org/ ?

[Altera_Forum]

There you go: http://demo.ovh.org/en/b37a9f9c4fbbf111438bd0e0a029708f/ 

But if you just add the A2 pin to your design it should work too.

[Altera_Forum]

Thanks a lot, Daixiwen. It works now.  

Very sorry for crashing your 9.0 Quartus since I am using 9.1 version and sincerely hope this will not cause you a greate trouble.

[Altera_Forum]

Hi, Daixiwen, 

When I tried to change the reading code to writing code, as attched, (change ssram_d from input to output) according to the datasheet.  There is the following error. In this code, I am trying to write datastream of 00000000h,00000001h,00000002h...into the memory, but when I verified the contents of SSRAM, I found only last four insignificant bits are correct, the higher 4 bits is not 0000h in the first addresses.  Could you please have a look at this?  Thanks again.

[Altera_Forum]

Don't worry, it wasn't too much trouble ;) 

I just realized I didn't pack the project properly, and the design files are missing. Here is the bdf I modified, if you just replace yours with this one and assign ssramclk to pin A2 it should work. But you managed to make it work anyway so I guess you don't need it ;)  As for your write problem, it may come from the fact that you are sometimes putting the D register to high impedance ('Z') while bwe_n is still 0. On that clock cycle, the SSRAM can really write anything. You should modify your code, either to invalidate the write operation when the D register is all Z's, or have one write per clock cycle (the ssram clock).