Can't explain why the required tsu be larger than the actual one

[Altera_Forum]

In Classic Timing Analysis, the equation of the slack is Required-actual,it is OK when it is positive and its not when negative. From the configuration of the tsu in quartus ii, we get that we can define the maxium ,not the minium ,of the its value.I am wandering why,because,you know,the longer,the better for the tsu in the condition of not surpassing the clock period. 

Any comments will be OK.

[Altera_Forum]

--- Quote Start ---  In Classic Timing Analysis, the equation of the slack is Required-actual,it is OK when it is positive and its not when negative. From the configuration of the tsu in quartus ii, we get that we can define the maxium ,not the minium ,of the its value.I am wandering why,because,you know,the longer,the better for the tsu in the condition of not surpassing the clock period.  Any comments will be OK.  --- Quote End ---    Hi JohnRita,  defining a tsu should gurantee that the input data is capatured correctly by your FPGA. That means you have to consider the output timing of the source which drives yor FPGA ! Assuming that the source devcie and the FPGA are driven by the same clock and the clock delay is 0:  clkperiod 20ns driving device tco 5ns  That means the data at the inputs of the FPGA are stable 5ns after the rising clock edge. With a clockperiod of 20ns your FPGA has 15ns left as setup time.  Kind regards  GPK

[Altera_Forum]

Hi,pletz, 

 Glad to receive your reply.What I said is within the FPGA,no driving source,except the power supply device.What I mean is that we should define the minimal value,not the max one,cause that the setuptime is a margin that the much the better.So the slack should be actual - required. regards

[Altera_Forum]

--- Quote Start ---  Hi,pletz,   Glad to receive your reply.What I said is within the FPGA,no driving source,except the power supply device.What I mean is that we should define the minimal value,not the max one,cause that the setuptime is a margin that the much the better.So the slack should be actual - required. regards  --- Quote End ---    Hi,  tsu and tco settings define the requirements for the inputs and outputs of the FPGA. They are not used for the internal timing. The internal setup and hold requirements are handled by Quartus itself by defining the required clock speed.   Kind regards  GPK

[Altera_Forum]

I see,Thanks a lot,pletz. 

I have see many definations of tsu,some of them have different meanings. In quartus, now I know,tsu is not the margin but the delay time,the equation of it is <data delay>+<micro setup delayed>-<clock delay>. It's different from I learn from textbook.