Hello, i made a FIFO from the MegaWizard and imported some pins inside SOPC Builder.
Basically i have rdreq and Q signals inside of my SOPC Builder and all others signals outside.
I have instanciated my SOPC systme like this
//fifo
.clock_to_the_novoFifo_0 (CLOCK_50),
.data_to_the_novoFifo_0 (data_in),
// .empty_from_the_novoFifo_0 (empty_from_the_my_fifo),
.full_from_the_novoFifo_0 (wrfull),
.almost_full_from_the_novoFifo_0 (wralmostfull),
.in_port_to_the_pio_0 (pio),
.wrreq_to_the_novoFifo_0 (wrwrreq)
); I am trying to get the almost_full and full_signals but they are always 1, why?
I am writting in my fifo like this:
if(full==0)
begin
wrreq <= 1;
FIFO_DATA <= FIFO_DATA+1;
if(almostfull)
pio<=1;
end
if(full==1)
begin
wrreq <= 0;
end but almostfull and full signals are always 1, really weird.
Both my SOPC Fifo and my Always block that writes inside it have the same clock (50 mhz).
