Quartus puts in its own blocks

[Altera_Forum]

When I try writing a decoder circuit in Verilog, in the RTL viewer I see that Quartus has inserted its own block called "Decoder". A simple bitwise Exor is replaced by Add0, Add1 and so on. 

 All this is OK, the only problem is that these elements [Decoder, Add0, Ram0] do not show up in the "Chip Planner".  Questions - 1. How do I tell Quartus NOT to interpret my design and put in Adders, Decoders and RamCells? 2. If not in the chip planner, where do these things go?  Thank you! ~E.

[Altera_Forum]

Quartus knows the best implementations for common blocks (decoder, MUX ...). They will be separated from random logic for special treatment. So it recognized your decoder as a decoder. By the end of the line everything gets converted into FPGA cells. It is normal to see structures come and go as the circuit is processed. 

 Is there some reason you don't want it to recognize the decoder? People usually complain about NOT recognizing circuitry.