Will DSP module be call directly in nios2 C app?

[Altera_Forum]

We all known there're a number of 9*9 mutiplier dsp module in CycloneII device. 

I build a nios2 system based on CycloneII and I wanna to call this 9*9 mutiplier in my nioseII C application, using * operator for simple,instead of using custom instruction.When I build this noisII system in SPOC builder, I already set CPU to use Embedded mutiplier.  Is that enough? Will I need others attention to realize what I want?

[Altera_Forum]

--- Quote Start ---  originally posted by markman@Apr 5 2006, 03:50 AM we all known there&#39;re a number of 9*9 mutiplier dsp module in cycloneii device. i build a nios2 system based on cycloneii and i wanna to call this 9*9 mutiplier in my nioseii c application, using * operator for simple,instead of using custom instruction.when i build this noisii system in spoc builder, i already set cpu to use embedded mutiplier.   is that enough? will i need others attention to realize what i want? <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14047)  --- quote end ---    --- Quote End ---    Why would you want to use a custom instruction for multiplication? The Nios2 already includes several mul(xxx) opcodes that calculate 32x32 multiplication. (see "Nios2 Processor Reference Handbook" chapter 8 "Instruction Set Reference") And the compiler uses these opcodes when you write a (integer) multiplication in c.  And I think the "embedded multiplier" setting tells sopc builder to use DSP Blocks instead of logic elements to implement the multiplication opcodes.

[Altera_Forum]

Hello wpaulus: 

Thanks for your help. There is "mul" instruction in nios2 system and I found as follow:  mul multiply Operation: rC &#8592; (rA × rB) 31..0 Assembler Syntax: mul rC, rA, rB Example: mul r6, r7, r8 Description: Multiplies rA times rB and stores the 32 low-order bits of the product to rC. The result is the same whether the operands are treated as signed or unsigned integers.  While we know the Nios2 instruction set is RISC, lots of clock cycles may needed when doing multiplication.What puzzled me was the introduction on page 15 of "Nios2 Processor Reference Handbook"  The Nios II processor is a general-purpose RISC processor core, providing: &#9632; Full 32-bit instruction set, data path, and address space &#9632; 32 general-purpose registers &#9632; 32 external interrupt sources &#9632; Single-instruction 32 × 32 multiply and divide producing a 32-bit result &#9632; Dedicated instructions for computing 64-bit and 128-bit products of multiplication &#9632; Single-instruction barrel shifter   Does the content means CAN doing a 32 × 32 multiplication in ONE clock cycle? Unfortunately, my work based on nios2 system is REAL TIME applitcation, in another word, that is time limited. And I need to do a 32 × 32 multiplication in 1 clock cycle for the best!  What&#39;s the worst, "mul" is one of "Unimplemented Instructions" as presented page 24 of "Nios2 Processor Reference Handbook" as follow:  Unimplemented Instructions Some Nios II processor cores do not provide hardware to perform multiplication or division operations. The following instructions are the only operations that the processor core may emulate in software: mul, muli, mulxss, mulxsu, mulxuu, div, divu. In such a core, these are known as unimplemented instructions. All other instructions are implemented in hardware. The processor generates an exception whenever it issues an unimplemented instruction, and the exception handler calls a routine that emulates the operation in software. Therefore, unimplemented instructions do not affect the programmer’s view of the processor.  What can I do now? Custom Instruction?

[Altera_Forum]

--- Quote Start ---  originally posted by markman@Apr 7 2006, 02:59 AM   what&#39;s the worst, "mul" is one of "unimplemented instructions" as presented page 24 of "nios2 processor reference handbook" as follow:  unimplemented instructions some nios ii processor cores do not provide hardware to perform multiplication or division operations. the following instructions are the only operations that the processor core may emulate in software: mul, muli, mulxss, mulxsu, mulxuu, div, divu. in such a core, these are known as unimplemented instructions. all other instructions are implemented in hardware. the processor generates an exception whenever it issues an unimplemented instruction, and the exception handler calls a routine that emulates the operation in software. therefore, unimplemented instructions do not affect the programmer’s view of the processor.  <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14120)  --- quote end ---    --- Quote End ---    You seem to be confused this says that mul is not implemented in some Nios II processors, whether you have a hardware Mul depends on the type of processor you use. That said the mul instruction is more than one cycle I can&#39;t remember how many off the top off my head

[Altera_Forum]

Hello markman, 

 sorry for the late reply, but I was out of office last week.  The speed of the multiplication instruction depends on the nios2 core you select, when designing the system (there are 3 : fast, standard, economy). On top of that you can disable the hardware for multiplication altogether. This is what unimplemented opcode means. You can find a table with the information on multiplication in the Nios2 Processor Reference Handbook under the section Appendix II.Nios2 Core Implementation Details, then look under the heading of your core.  About 32x32 multiplication in 1 cycle: As I understand it, the result of a 32x32 multiplication is 64bits long. As the nios2 is "only" a 32bit processor the result can&#39;t be stored completely in one register. Because of that there are the the different types of mul(xx). One instruction to calculate the lower 32bits of the result, and depending whether your operands are signed or unsigned, the mulx(??) instruction to calculate the higher 32bits of the result.  And to give my 5 cents about your question: If you need your 64bit result in 1 cycle, then I think you should use a custom instruction.