Critical Warning: Timing requirements for slow timing model timing analysis were not

[Altera_Forum]

Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details. 

I use the EP2C8Q208C8 FPGA board to design a progamm.When I use the LPM PLL to generate the signal of frequency 30, 50M,10M,however when compiled the Critical Warning:" Timing requirements for slow timing model timing analysis were not met. See Report window for details." is displayed.Why? Any Information or pointers to literature would be welcome.

[Altera_Forum]

This warning indicates that your design (most likely) has a register to register path that exceeds the clock period. The message implies that your chip will possibly not function as intended if you program it. I say "possibly not function" since the timing model reports worst case operating conditions. The device may function at room temperature with an ideal power supply. 

 By consulting the timing report window, you will find out which path(s) are violating their requirements. This may result in one or more of the following actions:  * fixing false paths that are incorrectly constrained  * changing place & route optimization settings  * altering the design to meet timing requirements  * etc...  Timing closure is (sometimes) a very complicated problem. Without knowing more information about your particular design and/or failing paths, it is difficult to provide additional information.  - Mark

[Altera_Forum]

Thanks a lot for your reply! 

Now I upload my design .My design is about electron pair bond spectrometer . The design scheme is using FFT IP CORE to generate real parts and imaginary parts ,then stored in two FIFO,at last using UART to send to PC.At the begining ,the data from AD board ,I stored the data in one FIFO too. The solution of the design's control is separated.The real part and imaginary part FIFO's empty and full controls the clock of the FFT, the ad data FIFO's empty &full controls the AD board's clock (in another way controls the data samlping),and the FIFOs ' used signal is used to reset FFT to start . That's all ,for other more information please contact me .My email is hjwy111@yahoo.com.cn Any Information or pointers to literature would be welcome. The file is too big ,so I dived it into 3 to upload ,when using you must put them together. Oh ,the most important is that the QUARTUS is 7.2,megacore 7.2,matlab 7.4.

[Altera_Forum]

The upload speed is too slow to tolerate ,somtimes can not upload .So I think use another way maybe right .Could you leave your email address for me ?

[Altera_Forum]

If anyone want a copy of my design ,please contact me . 

Email:hjwy111@yahoo.com.cn

[Altera_Forum]

It sounds like you are new to Quartus. For information about the Quartus timing analyzer, see the chapter for the analyzer you are using (Classic Timing Analyzer or TimeQuest) in the Quartus handbook, Volume 3, Section II. The handbook is available at http://www.altera.com/literature/lit-qts.jsp. (The handbook on the web site is for version 8.0. If you are using a recent pre-8.0 Quartus version, most of the information in the 8.0 handbook will apply.) 

 After you have the design constrained correctly including any false paths (mentioned by Mark) and multicycles, use "Tools --> Advisors --> Timing Optimization Advisor" in Quartus to get suggestions for fixing timing violations.

[Altera_Forum]

--- Quote Start ---  This warning indicates that your design (most likely) has a register to register path that exceeds the clock period. The message implies that your chip will possibly not function as intended if you program it. I say "possibly not function" since the timing model reports worst case operating conditions. The device may function at room temperature with an ideal power supply.  By consulting the timing report window, you will find out which path(s) are violating their requirements. This may result in one or more of the following actions:  * fixing false paths that are incorrectly constrained  * changing place & route optimization settings  * altering the design to meet timing requirements  * etc...  Timing closure is (sometimes) a very complicated problem. Without knowing more information about your particular design and/or failing paths, it is difficult to provide additional information.  - Mark  --- Quote End ---    thank you a lot.