Hello, all!
I'm trying to create memory cache controller in Verilog from scratch. I'm using QuartusII 10.0 Web Edition under Linux.
Cache controller consists from 2 memory modules (based on the internal M4K memory), some logic and finite-state machine (16 states).
Recently I've ran into a problem: compiling process hangs consuming 100% of CPU - quartus_map process after some time of running consumes more than 2Gbytes of memory and swap and then I terminate the compiling process.
I've tried to remove FSM from the code completely and compile rest of code. This produces a lot of warings, but compiles ("Analysis & Synthesis" task marker green and message box appeared). Then I've tried to remove logic and memory and compile only FSM (really I've just marked FSM as top-level module - it is in separate file). It compiles too. Then I've commented all states in the original unmodified code and started uncommenting them by one and compiling. I've found one state, uncommenting which lead to compiler's hang. But this state is like other states syntactically and logically - it is not a 'special' state.
Now I think that it is a bug in the compiler.
Can anyone help me with this issue?
Project attached, top-level module is sora_cache_sa, FSM module is sora_cache_sa_fsm. To reduce size of archive I've deleted contents of db/ and incremental_db/ directories.
Best regards, Alexander.
