Run a ACEX 1K with a 33% (or 66) duty cycle clock?

[Altera_Forum]

Hi everybody, 

 My concern is:  Is it possible to run a ACEX 1K with a 40 MHz clock at duty cycles lower/upper than 40-60% (recommended into the Altera datasheet)?  I would like to clock the fpga from a 60MHz clock divided by 1.5, but this division outputs a duty cycle which is 33% (or eventually inverted 66%).  Thanks in advance for any answers,  -Pierre

[Altera_Forum]

I would not violate the specs. 

 And why not run it at 60 MHz?

[Altera_Forum]

Hi Avatar, 

 At 60Mhz, I have problems fitting my current design with the -3speed grade (fits up to 50Mhz or so).  The thing is when you divide a frequency F by 1.5 by logic means (flip-flops and combinatorial), the F/1.5 output has a dutycycle of 33%. Or 66% is you invert the clock. I don't think you can convert a 50% F clock into a 50% F/1.5 clock without using a PLL.  The ACEX1K datasheets mention a 40-60% dutycycle spec, but seems to be only the case when using the -1/-2 speedgrade-related integrated PLL. I am currently working with the slower -3 speedgrade which has no such PLL.   Eric (newest member, and the originator of the post, thanks Pierre for the typing :) )