Output Enable Groups

[Altera_Forum]

What is the purpose of assigning an output enable group to my DDR2 DQ and DQS signals, and will Quartus do this automatically?

[Altera_Forum]

When implementing a DDR2 interface, you will be using I/O that reference a VREF voltage. It is important that the VREF pins that support these signals are not affected by noise. Thus there are limits imposed by Quartus to the number of pins that a VREF pin can support.  

Each output pin adds some noise to the VREF level and so a large number of outputs make the level too unstable to be used for incoming signals.  Thus it is important to remember that, as the DQ/DQS pins are bidirectional, and reference VREF when inputs, Quartus does not know that they will either all be outputs or all be inputs at any one given time.. By default Quartus assumes that, during one particular transaction, some DQ/DQS signals could be outputs whilst others are inputs and based on this, you could violate the placement rules and your design will fail to compile.  Thus, DQ & DQS of a particular memory interface should considered as being part of the same 'output enable group' and you must explicitly assign an output enable group number to these signals in Assignment Editor, so that invalid VREF to I/O related placement errors are not given.

[Altera_Forum]

Does this VREF problematic mean that a cyclone III (ep3c120 for me) with 6 Vref group on bank 3/4 will not support a 32 bit DDR2 Controller when using this two banks only? 

 Each VREF group can have max 9 outputs/bidir, meaning that only 6*9=54 output are available on bank 3/4, which is not enough for the 72 pins necessary to the 32 bit DDR2 controller? What do you mean?  FLo

[Altera_Forum]

I think I understand the concept of "Output Enable Groups". But is there a way of setting such without using a tcl-script? And how can I check in the pin assignment editor, which pins have been assigned to such groups?  

 Thank you for your help!