CPLD: measuring the performances

[Altera_Forum]

We have programmed our CPLD and now we would like to test if our design is valid and the system performances. I am just writing and reading values in our registers and checking if it is Ok, but I would like to know if there is any trick or any weakness in the device (it is a MAX II) that it is good to know in order to write the benchmark or the testing program.  

 P.S. I asked some weeks ago the possibility of making the In System Programmability using a 8051 with my MAX II, it was very problematic; we gave up, but if somebody knows a way as the people says in my country it’s better later than never.

[Altera_Forum]

If I need to confirm if the CPLD is working fine (in user mode), I would assign one of the pins to low in my design. If the device does not go into user mode, the I/Os should be tristated with weak pull up.

[Altera_Forum]

Or you can connect the output pin to the internal ocsillator of the MAX II device and when the device goes into user mode, you should see the output pin toggling at around 5MHz. You can intantiate the oscillator with the alt_osc megafunction.