syntax errors.

[Altera_Forum]

I'm getting this error: 

Error (10500): VHDL syntax error at processor.vhd(53) near text "PORT"; expecting "(", or "'", or "." I'm not sure why but here's the relevant code:  The error refers to the line: fetch: imem PORT MAP(PC1,PC2,clock,INS1,INS2,0,0,INS1,INS2);--fetched the INS  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; use work.all; entity processor is port ( clock,reset : in std_logic; keyboard_in : in std_logic_vector(15 downto 0); keyboard_ack : out std_logic; lcd_out : out std_logic_vector(15 downto 0); lcd_write : out std_logic ); end processor; architecture a of processor is TYPE State_type IS(A,B,C,D,E); SIGNAL state: State_type; SIGNAL PC1,PC2,INS1,INS2: STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL opcode: STD_LOGIC_VECTOR(3 DOWNTO 0); COMPONENT imem IS PORT ( address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0); address_b : IN STD_LOGIC_VECTOR (12 DOWNTO 0); clock : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0); wren_a : IN STD_LOGIC := '1'; wren_b : IN STD_LOGIC := '1'; q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END COMPONENT; begin process(clock,reset) begin if(reset = '1') then state<=A; PC<="0000000000000000"; --initialize stuff elsif(rising_Edge(clock)) then case state is when A=> fetch: imem PORT MAP(PC1,PC2,clock,INS1,INS2,0,0,INS1,INS2);--fetched the INS opcode<=INS1(15 DOWNTO 12); state <= B; when B=> --etc... end case; end if; end process end a;

[Altera_Forum]

Your instantiating a component in sequential code (a process). Components can only be instantiated in concurrent code.

[Altera_Forum]

I'm confused... I have to be able to use components and I also need to use a process block, otherwise I can't access any of my stuff.

[Altera_Forum]

Hello, 

 a instantiation of a component is structural code, your defining memory hardware with in- and output signals. The hardware exists also outside a state A and the signals have to be supplied anyway, unconditionally. But you can instantiate the component outside the process. Wren or an optional rden could be used to create condtional memory operation, if necessary.  Regards, Frank

[Altera_Forum]

Sorry I'm just not following. I can't take my fetch: statement outside the process block because the fetch needs to operate on the clock. I can't take away my process block because then nothing is operating on the clock. I'm basically trying to design a processor using vhdl and components that I've made already

[Altera_Forum]

You basically don't need to change the structure of your code, but move the memory instance to concurrent code section (where it has to be by VHDL specification). You can generate addresses and control signals for the memory instance from process and interface the input and output data. That's how any known combination of processes and concurrent code works.

[Altera_Forum]

So you're saying I have to move this: 

fetch: imem PORT MAP(PC1,PC2,clock,INS1,INS2,0,0,INS1,INS2);--fetched the INS somewhere else?  I'm not sure where to put it since I need the fetch to happen everytime I'm in that state, not only once or everytime, just at certain times.

[Altera_Forum]

The hardest thing about learning any HDL is learning to think in non-sequential terms. You seem to be seeing your imem component as a function call. Each entity in your VHDL describes a piece of hardware that operates concurrently with all the other hardware components. Just instantiate the component outside the process. Yes, it means that you will always fetch from the instruction memory on every clock edge. By fetch, I mean, you will always read from the memory. So what? What matters is when you use the memory outputs q_a and q_b and update the program counters. You're state machine controls this behavior.

[Altera_Forum]

Ok, that makes sense i guess. I changed my code to look like this and it compiled: 

begin fetch: imem PORT MAP(PC1,PC2,clock,INS1,INS2,'0','0',INS1,INS2);--fetched the INS process(clock,reset) begin if(reset = '1') then state<=A; PC1<="0000000000000000"; --initialize stuff elsif(rising_Edge(clock)) then case state is when A=> opcode<=INS1(15 DOWNTO 12); state <= B; --other stuff   The problem I'm forseeing is when I want to do decode. Initially I was thinking of a bunch of opcode sensitive if statements and then decode depending on what opcode I have but since I can't put port maps into my process block I'll have to put it outside but I guess its up to the state machine to make sure I set the right values?

[Altera_Forum]

I think you're getting the idea. Did you build a decode entity? A simple decoder is nothing more than a chunk of combinational logic that takes the opcode as input and asserts control signals. Again, in a real hardware system, one doesn't think in terms of "only execute this function at a particular point in time". A chunk of combinational logic always reacts to changes in its inputs and that's OK. It only matters that the comb logic has the correct inputs when you care about (read: sample) the outputs.  

 Your state machine is responsible for controlling the flow of data between your different hardware blocks. For example, in the fetch phase, it stores the current instruction's opcode in the opcode register. This register feeds the decoder, which generates a bunch of control signals that you can register on the next clock cycle. At least, this is how it might work if you were building a pipelined processor.

[Altera_Forum]

Hello, 

 it must be considered well, if an assignment as opcode<=ins1(15 downto 12); should be placed in clock synchronous process code, which implies a register, that doesn't immediately get the new value or if only a kind of alias for the bitgroup is intended. You should understand also the timing and the possible options (e. g. registered versus unregistered output, clken, wren and rden signals) of internal memory block.  Regards, Frank