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Design for Multiple NIOS II

Altera_Forum
Honored Contributor II
‎07-05-2009 08:54 AM
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A question regarding consideration in HW design for best supporting (and best performance) of multiple NIOS II architecture. E.g: 

 

* extrenal RAM accessed by multiple NIOS II CPUs : are performance degraded when accessed in parallel by several NIOS II CPUs? Is there a recommendation how tol solve it (multiple RAM chips/controllers) ? 

* BUS limitations : what BUSes willsuffer from performance degradation due to the load of several CPUs ? How to solve ?  

*External arbitters required ? 

* ANy other comments / recommendations ? 

 

Thanks, 

 

Hed.
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Altera_Forum
Honored Contributor II
‎07-09-2009 02:12 AM
202 Views

You should consider reading 

Computer Architecture, Fourth Edition: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design) by Hennesy and Patterson 

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