Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Schematic project, rom clock!

Altera_Forum
Honored Contributor II
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Hello! I am making a little project with blocks and everything else, a schematic project. (Quartus II 8.1 web edition) 

 

I am using the lpm_rom. I would like to use a memory that with one clock gets the address and output the result, is there a solution for this? I am getting some troubles to synchronize my system, but this would be a good solution. 

 

Thank you!
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Altera_Forum
Honored Contributor II
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lpm_rom can be operated with registered address and unregistered output, this means a latency of one clock cycle between address input and data output. Is this what you intend? Asynchronous (no-latency) operation isn't provided.

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