Hello All,
I am building a system where I wish to boot a NIOS II processor from the 32M RAM onboard a DE0-nano system, and hope that someone may have already created a wiki/example/tutorial on the subject.
So far, the SDRAM has been attached, and appears to be accessible from a small NIOS system running in internal FPGA RAM.
Hardware, and boot loader: I have found an example of a boot loader which needs to run out of internal FPGA RAM, but appears to use an SPI interface to talk to the EPCS boot FLASH. I was rather expecting an EPCS interface would be more appropriate.
Boot loader compile options: Presumably it is possible to hard-wire a selection of EPCS load addresses into the boot code, so one of several software modules could be booted into SDRAM, with the selection being made at boot time.
Software development environment: Since the task running out of SDRAM will have a run address outside of internal FPGA RAM, a method is required to either generate position independent code, or to pass an absolute link/load address to the compiler.
EPCS programming: The normal GUI based work flow (using Convert Programming file) is easy enough to allow a JIC file to be created from an SOF. How does one add additional software files for booting, and what are the associated parameters.
Currently using Quartus 12, for reasons of legacy support.
Thoughts and comments please.
Many thanks, Mark
