Reconfigurate the FPGA image from the Nios II software

[Altera_Forum]

Hi 

  Is it possible to reconfigurate the FPGA from the EPCS device with a command on the NIOS II?   Thanks for help

[Altera_Forum]

It amounts to suicide, if nios can drive the nConfig

[Altera_Forum]

Yes it amounts to suicide, but that's no problem for me. 

I use it to load a new hardware configuration from the EPCS which is remote updated.  So it's only possible with additional hardware on the PCB? In this case I need a FPGA output to drive the nConfig?

[Altera_Forum]

Naturally, you need to drive the configuration pin from fpga if you want nios to a have a go into the unknown afterlife. 

 Are you sure your new nios will tick again, consider having a default image that is never touched(sacred image) just in case of emergency especially with remote applications.  edit:  Make sure that the user at their premises can reconfigure the fpga e.g. from board jumpers in case the new remote didn't work otherwise you have to fly there with your full gear unless a default image is loaded automatically.

[Altera_Forum]

what fpga are you using? all of the stratix devices can suicide with internal logic by use of the remote update block, this is true for cyclone 3 as well, i would have to check cyclone 2, but it is not possible without external logic on cylone I. 

 --dalon

[Altera_Forum]

Yes, you can load a new image into the EPCS via the NIOS. Then when you are finished, you use the remote update controller to trigger a reconfig of the FPGA. We do this all the time. 

 Jake

[Altera_Forum]

There is some further discussion of this in the NIOS forums. Altera provides a "Remote Upgrade" megacore that controls the config signal, so you don't need to add external connections or logic to do it. In Cyclone III, Altera even provides an SOPC wrapper. 

 Since this is almost always done with NIOS, I don't know why they didn't provide a SOPC wrapper in other families. They really ought to!  "Remote upgrade" is a slight misnomer - to me, that implies the process of getting a modified image into the EPCS, and not the mechanism that triggers a re-config.  In Stratix II, the megacore doesn't work properly if clocked at 166 MHz, but does at 33MHz... I don't know what the legal clock rate is.

[Altera_Forum]

I've provided a simple core with some simple software hooks for the Stratix II and Stratix II GX series in the shared material section of the forum.

[Altera_Forum]

Thanks for all the help. 

 I will try some tests with your information.   @jakobjones: What's the name of your project in the shared material section of the forum?     Thanks to all

[Altera_Forum]

http://www.alteraforum.com/forum/showthread.php?t=3658