SDRAM for program code

[Altera_Forum]

HI (again) 

 I’m bulding a multiprocessor system with 2 cpu’s, using 2x Jtag Uart, SDRAM for program memory and 2x onchip memory blocks for rwdata and a dualport memory for communication between the cpu’s.  The system compiles but when trying to debug the system with the standard “Hello World” application, I run into problems.  My setup is: (Using Nios dev. Kit 1S10, Quartus 4.2 we and NiosII 1.1 eval )  SDRAM:   Base address: 0x0 End address: 0x00FFFFFF  CPU 0:  Reset address: 0x00B000000 Exception address: 0x00C000020  CPU 1:  Reset address: 0x00D000000 Exception address: 0x00E000020  IDE:  .text an .rodata are set to SDRAM .rwdata are set to onchip memory   When running debug for a single CPU ( not multiprocessor collection) I get the following message when connecting to the debug module after the code is uploaded:  warning cannot insert breakpoint 1 error accessing memory address 0xc00360 (undocumented errorno: -1)  Have tried to debug several projects but get the same message, except pointing at different memory addresses.  Any help?  Going trough the summary from the “Fitter”(QuartusII) I found the following warnings:   warning: can't pack node multicpu2:inst|sdram:the_sdram|za_data[24] to i/o pin  warning: can't pack register multicpu2:inst|sdram:the_sdram|za_data[24] -- no packable connection to input pin warning: can't pack node multicpu2:inst|sdram:the_sdram|za_data[15] to i/o pin  warning: can't pack register multicpu2:inst|sdram:the_sdram|za_data[15] -- no packable connection to input pin warning: can't pack node multicpu2:inst|sdram:the_sdram|za_data[23] to i/o pin  warning: can't pack register multicpu2:inst|sdram:the_sdram|za_data[23] -- no packable connection to input pin warning: can't pack node multicpu2:inst|sdram:the_sdram|za_data[7] to i/o pin  and so on…..  Thanks   Stian

[Altera_Forum]

In my Opinion your CPU-addresses (reset and exception) have to point to some kind of memory. If you want to execute code from your sdram, maybe the exception addresses should point to that device?! 

 I'm using the cyclone developement board and the documentiation for that device points that code-execution is started from the given exception-address...  May be, you should also take a look at "NIOS II Software Developer's Handbook" section 4-30 Memory Usage for that topic...

[Altera_Forum]

Hi 

 By editing the Standrad sytem example that was included in the NiosII kit I got it working.  I guess I needed the PLL that ensures timing adjustments for the SDRAM device.  Stian

[Altera_Forum]

That's correct. On your board you need a 3.5 ns delay (phase shift of -3.5ns). This compensates for the board delays in the clock networks.

[Altera_Forum]

What do the warnings mean? I've ignored them. 

 <div class='quotetop'>QUOTE </div>  --- Quote Start ---  Warning: Can&#39;t pack node Multicpu2:inst|sdram:the_sdram|za_data[24] to I/O pin Warning: Can&#39;t pack register Multicpu2:inst|sdram:the_sdram|za_data[24] -- no packable connection to input pin Warning: Can&#39;t pack node Multicpu2:inst|sdram:the_sdram|za_data[15] to I/O pin Warning: Can&#39;t pack register Multicpu2:inst|sdram:the_sdram|za_data[15] -- no packable connection to input pin Warning: Can&#39;t pack node Multicpu2:inst|sdram:the_sdram|za_data[23] to I/O pin Warning: Can&#39;t pack register Multicpu2:inst|sdram:the_sdram|za_data[23] -- no packable connection to input pin Warning: Can&#39;t pack node Multicpu2:inst|sdram:the_sdram|za_data[7] to I/O pin  and so on?.[/b]  --- Quote End ---  

[Altera_Forum]

Is Quartus telling you it can&#39;t pack all the signals or just a few? Also what optimizations do you have turned on in the Synthesis and Fitter options? 

 Basically it&#39;s telling you that it couldn&#39;t locate those registers "beside" the I/O pin. If those warnings are acompanied by any more info I would look into that as well.