Cyclone III, huge cap at VCCD_PLL

[Altera_Forum]

Hi All! 

 Altera document "Cyclone® III Device Family Pin Connection Guidelines PCG-01003-1.0" says that 470 uF capacitor must be used at digital power of PLL (besides a lot of ceramic capacitors). This is a bulk capacitor, as a rule such capacitor is low-frequency and intended for compensate a sagging of power supply. But VCCD_PLL begins from VCC_INT and no sagging presents.   What is the reason for using of such capacitor in VCCD_PLL circuit?   Best regards.

[Altera_Forum]

--- Quote Start ---  What is the reason for using of such capacitor in VCCD_PLL circuit?  --- Quote End ---  It doesn't sound reasonable. None of Cyclone III I'm working with has a similar capacitor. In my opinion, it should be expected, that the device manual is containing all respectice information. It tells    --- Quote Start ---  VCCD_PLL must always be connected to VCCINT through a decoupling capacitor and ferrite bead.  --- Quote End ---   The suggestion is also varied to "should always" in some places. Both versions sound reasonable.

[Altera_Forum]

Some interesting reads: 

http://www.altera.com/literature/an/an574.pdf http://www.altera.com/literature/an/an583.pdf  I would not use a 470uF bulk cap on the VCCD_PLL rail. With the amount of current you are likely to be drawing, you might at most put a 10uF ceramic (besides the high frequency bypass).  I typically put a 1uF a 10uF ceramic in addition to the high frequency bypass.   Jake

[Altera_Forum]

Altera directs to use this cap: 

 11) Decouple VCCD_PLL power island with a parallel combination of 1x470uF(low ESR Tantalum), 1x4.7uF, 5x0.1uF, 2x0.01uF, 1x0.0047uF, 1x0.0022uF.  This bulk cap is used for anti-resonance spike suppression. The spike comes from ferrite bead induction and decouple caps capacitance. This case is described in AN583, which link you gave in your post. Large 470 uF cap recommended, I think, to cover all cases. User can use cap with another value, but in this case the value should be calculated and/or modeled.  The answer is found. Thanks to all.  Best regards.

[Altera_Forum]

As AN583 reveals, the suggestion is only based on simulations results. I have serious doubts, if the assumptions meet a typical FPGA supply situation. Some lack of practical design experience can be suspected for the guy, who performed the simulation. But I'll check the resonance point with some real world circuits.

[Altera_Forum]

I think that the reason is real. PDN consists of several ceramic capacitors and its own resonanses are far from inductive component of bead impedance, so LC oscillation tank[s] takes place in any case. What do you propose to prevent negative influence of the parasitic resonances? IMHO, the using of large bulk capacitor is good enough solution.

[Altera_Forum]

I don't want to put you of using a 470 uF capacitor. As jacobjones, I just doubt it's necessity and reported, that I didn't yet use a similar value. But I'll check some common supply filter dimensioning if they actually show a low frequency resonance as assumed in the AN. For some reason, I don't expect this high low pass (or "antiresonance") Q. But I may me wrong. 

 As another point, that hasn't been addressed yet. It's no obvious in my opinion, that VCCD has a high susceptibility for interferences at all. It's pretty clear for VCCA, although pleasantly reduced with newer devices, that have an internal PLL voltage regulator. In practice, I only experienced PLL supply issues with 1.2V VCCA of older devices.

[Altera_Forum]

Take a look at some of the schematics for Altera development kits and see what they did. That might give you more of a "warm fuzzy". 

 Jake

[Altera_Forum]

--- Quote Start ---  Take a look at some of the schematics for Altera development kits.  --- Quote End ---  Yes, the present cyclone III Dev Kits are ignoring even most device manual suggestion about supply decoupling. You may want to do more.  It should be also mentioned, that the said AN583 is basically targetting to Stratix IV with 10 GBit transceivers rather than gentle Cyclone III.