Flash programming for DE2-70

[Altera_Forum]

Hello Friends, 

  This is a common problem here in the forum. However, Ihaven't been able to make heads nor tails out of it. I'm trying to program the sof file by EPCS and the OS in the CFI Flash.  I'm running the system in a DE2-70 board with a Nios II/f processor.  Below is my configuration for SOPC  ext_flash base=0x00000000 end=0x007fffff epcs_controller base=0x00e05800 end=0x00e05fff  on the cpu SOPC: reset vector offset 0x0 in ext_flash   Then I compile the project. Everything seems fine.  I am first trying to boot the default image to uclinux, because when I tried to change some things in SOPC builder, I had to rebuild almost everything, so I decided to go step by step. I built the default configuration BUT added MTD suport following:  http://www.nioswiki.com/mtd  QUestion 1) If I only have the CFi flash, do I only need to enable that one? No need for SPI FLash or NAND flash, right?   # ### To enable MTD Memory Technology Device (MTD) support ---> --- Memory Technology Device (MTD) support Debugging (NEW) MTD concatenating support (NEW) MTD partitioning support RedBoot partition table parsing (NEW) Command line partition table parsing (NEW) TI AR7 partitioning support (NEW) *** User Modules And Translation Layers *** Direct char device access to MTD devices -*- Common interface to block layer for MTD 'translation layers TI AR7 partitioning support (NEW) *** User Modules And Translation Layers *** Direct char device access to MTD devices -*- Common interface to block layer for MTD 'translation layers Caching block device access to MTD devices # ### To enable CFI flash RAM/ROM/Flash chip drivers ---> Detect flash chips by Common Flash Interface (CFI) probe Detect non-CFI AMD/JEDEC-compatible flash chips (NEW) Flash chip driver advanced configuration options (NEW) Support for Intel/Sharp flash chips# for neek Support for AMD/Fujitsu flash chips# others Support for ST (Advanced Architecture) flash chips (NEW) Support for RAM chips in bus mapping (NEW) Support for ROM chips in bus mapping (NEW) Support for absent chips in bus mapping (NEW) Mapping drivers for chip access ---> Support non-linear mappings of flash chips (NEW) <*> Flash device in physical memory map Physmap compat support Generic uClinux RAM/ROM filesystem support (NEW) Map driver for platform device RAM (mtd-ram) (NEW) # ### To enable flash filesystem support File systems --> Miscellaneous filesystems ---> Journalling Flash File System v2 (JFFS2) support # ##### end of kernel config # ### user application config Flash Tools ---> --- MTD utils mtd-utils eraseall   I didn't quite understand what modifications should be made in  linux-2.6/arch/nios2/kernel/config.c but I guess none since I am using a Cyclone 2 chip.  After that, I follow number 1 in: http://www.nioswiki.com/operatingsystems/uclinux/flashprogrammer   I program up to the HW and it works correctly. But when I try to create the CFI Flash image I get the following:   $ elf2flash --base=0x00000000 --end=0x007fffff --reset=0x0 --input=/home/pancho/nios2-linux/uClinux-dist/images/zImage --output=ext_flash.flash --boot=/opt/altera8.1/nios2eds/components/altera_nios2/boot_loader_cfi.srec ~/nios2-linux/uClinux-dist $ nios2-flash-programmer --base=0x0 ext_flash.flash Using cable "USB-Blaster ", device 1, instance 0x00 Resetting and pausing target processor: OK Checksummed/read 28kB in 0.5s Erased 1472kB in 5.3s (277.7kB/s) Programmed 1445KB +27KB in 14.2s (103.6KB/s) Device contents checksummed OK Leaving target processor paused ~/nios2-linux/uClinux-dist $ nios2-terminal nios2-terminal: connected to hardware target using JTAG UART on cable nios2-terminal: "USB-Blaster ", device 1, instance 0 nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)   And it never boots. I am using DE2_70_NET example. But I don't think there are hardware problems over there in any connections. If someone has used it please let me know if he/she was able to use it 'as is'.   Hope this information is enough to see the problem. I can post any information that might be neccesary.  Thank you all  Francisco 

[Altera_Forum]

Please check the cpu reset vector of in sopc builder. It was set to onchip_mem in the demo design. You will need to change it to cfi flash. 

 - Hippo

[Altera_Forum]

Hello hippo,  

 The reset vector on SOPC builder is set to "ext_flash" at 0x0. This is the name indicated in  http://www.nioswiki.com/mtd  is this name ok? or should I change it for 'cfi_flash' or 'cfi_flash_0' ?  should I disable the onchip-mem? But I guess there is no problem as long as the reset vector points to the ext_flash?  The addresses for my system are: Below is my configuration for SOPC  ext_flash base=0x00000000 end=0x007fffff epcs_controller base=0x00e05800 end=0x00e05fff  on the cpu SOPC: reset vector offset 0x0 in ext_flash  I also checked the Data cache line size is set to 32 Bytes. I recall reading somewhere that this parameter should be set to 4 bytes, but don't know if this has got something to do with the problem. Besides, I was working on an Altera DE2, and now I'm working with a DE2-70, and 32 Bytes was set for the DE2_70_NET example. When running from SDRAM, there was no problem using 32-byte width.  my hardware selection  --- Please select which CPU you wish to build the kernel against: (1) cpu - Class: altera_nios2 Type: f Version: 7.08 Selection: 1 --- Please select a device to execute kernel from: (1) sdram_u2 Class: altera_avalon_new_sdram_controller Size: 33554432 bytes (2) onchip_mem Class: altera_avalon_onchip_memory2 Size: 8192 bytes (3) ssram Class: altera_avalon_cy7c1380_ssram Size: 2097152 bytes (4) sdram_u1 Class: altera_avalon_new_sdram_controller Size: 33554432 bytes (5) epcs_controller Class: altera_avalon_epcs_flash_controller Size: 2048 bytes (6) cfi_flash_0 Class: altera_avalon_cfi_flash Size: 8388608 bytes Selection: 6    If I 1)add the default configuration, and then 2)the MTD support and flash tools, should I be able to see the default config booting from flash using the commands?   I didn't change anything from altera.c or nios2.h, I believe those are some of the files that require modification?  when I do  elf2flash --base=0x00000000 --end=0x007fffff --reset=0x0 --input=/home/pancho/nios2-linux/uClinux-dist/images/zImage --output=ext_flash.flash --boot=/opt/altera8.1/nios2eds/components/altera_nios2/boot_loader_cfi.srec  is --reset the reset vector specified in the cpu?   and in  nios2-flash-programmer --base=0x0 ext_flash.flash  is --base the base address for the ext_flash?  Do I need to enable SPI and NAND flash as well? I am loading HW config into epcs and the OS to CFI flash. also from  http://www.nioswiki.com/mtd    --- Quote Start ---  The CFI flash component should be named as "ext_flash", and the EPCS controller component should be named as "epcs_controller", otherwise you have to modify linux-2.6/arch/nios2/kernel/config.c .  The mtd partition map is located in linux-2.6/arch/nios2/kernel/config.c . You will need to edit the maps and buswidth for your boards.   The EPCS controller is exactly an Altera SPI interface plus some onchip memory. And the EPCS flash is exactly SPI flash, so we use the SPI driver to access the SPI flash.    --- Quote End ---    These are some of the questions that come to my mind now  EDIT:  I also found on another thread the following suggestions  there are few things you need to look at: 1. open sopc builder and check your cfi controller is placed on 0x01400000 and exception is not given on cfi (if reset vector is on flash, it is ok) my exception vector is pointing to ext_flash as well. at offset 0x20. where should it point to?changed it to sdram 2. you have selected correct size and timing parameters in cfi controller which matches your flash device on board apparently this is done modifying altera.c and nio2.h this i haven't figured out yet.4. make sure flash programmer's current instance is taking reference of same nios project you are working on (else you just delete all instances of flash programmer and re instance again by selecting your working project) suppose this refers to cleaning the project and then make vendor_hwselect. if that's the case, done 5. check system library properties of nios ii project and make sure read/write memory, stake memory, heap memory are not falling into flash device. keep it in volatile device like sdram or ssram or onchip ram. no idea    Thank you very much.  Francisco

[Altera_Forum]

The cfi flash of de2-70 net design uses 16 bits mode. Please change line 323 .width to 2. 

 linux-2.6/arch/nios2/kernel/config.c  You may also change mtd map as 8MB flash at line 214, to,  0x400000, 0x400000,  0x400000, 0x000000   - Hippo

[Altera_Forum]

Hi hippo, 

  I made the modifications you suggested in /linux-2.6/arch/nios2/kernel/config.c  after that 

• make

• make linux image

• nios2-configure-sof /home/pancho/nuevos/DE2_70_cinco/DE2_70_NET.sof

• sof2flash --epcs --input=/home/pancho/nuevos/DE2_70_cinco/DE2_70_NET.sof --output=standard.flash

• nios2-flash-programmer --epcs --base=0x00e05800 standard.flash

• elf2flash --base=0x00000000 --end=0x007fffff --reset=0x0 --input=/home/pancho/nios2-linux/uClinux-dist/images/zImage --output=ext_flash.flash --boot=/opt/altera8.1/nios2eds/components/altera_nios2/boot_loader_cfi.srec

• nios2-flash-programmer --base=0x00000000 ext_flash.flash

$ nios2-terminal nios2-terminal: connected to hardware target using JTAG UART on cable nios2-terminal: "USB-Blaster ", device 1, instance 0 nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate) Nothing.    I am trying to see the console via JTAG UART because I will use the UART for other purposes. Is this possible?  How does the boot loader know that it has to load the OS specifically in SDRAM 1? where do I specify it? Because there is on-chip mem and two SDRAMs, as well as one SSRAM.

[Altera_Forum]

Hello all, 

  So I finally managed to boot from the CFI FLash. My mistakes were the following.    1) In hw_select I had to choose to boot from sdram, because I was choosing to boot from CFI Flash.  2) input instructions as follows.  $ elf2flash --base=0x00000000 --end=0x007fffff --reset=0x0 --input=/home/pancho/nios2-linux/uClinux-dist/images/zImage --output=ext_flash.flash --boot=/opt/altera8.1/nios2eds/components/altera_nios2/boot_loader_cfi.srec ~/nios2-linux/uClinux-dist $ nios2-flash-programmer --base=0x0 ext_flash.flash --go   Did the trick!  Thank you  Francisco

[Altera_Forum]

Great. 

 As you have mtd, you may also try to do it in another way to program cfi flash,  nios2-linux-uclibc-objcopy -O binary images/zImage zImage.bin  Boot uClinux, use ftp to transfer the file,  eraseall /dev/mtd1  cp zImage.bin /dev/mtd1  - Hippo

[Altera_Forum]

I successfully programmed SOF in EPCS and zImage in CFI Flash ! The board starts uClinux without any JTAG cable at powerup :-) 

 I tried your method to program CFI flash under FTP but I changed some commands...  ------------------------------------------------------------------ elf2flash --base=0x00000000 --end=0x1ffffff --reset=0x0 --input=zImage --output=zImage.flash --boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_cfi.srec  nios2-linux-uclibc-objcopy -Isrec -O binary zImage.flash zImage.bin # then copy zImage.bin to uClinux FTP with FileZilla for example  telnet 192.168.0.xxx root cd home/ftp flash_eraseall /dev/mtd1 cp zImage.bin /dev/mtd1 sync # finally master reboot and enjoy ! ------------------------------------------------------------------  Thanks for your help Hippo you're the best :D

[Altera_Forum]

Can you do a NiosWiki article on this ?  

 -Michael

[Altera_Forum]

This is great info for us DE2-70 users (who are often neglected in tutorials and configuration instructions). 

 I couldn't get uClinux booting either using my project that's based on the DE2_70_NET example. I finally got it when I read post# 6 which brought me to the conclusion that I had to tell the kernel image I wanted to run from SDRAM not CFI. I was really racking my brain on that.  So a couple highlights I want to point out about my configuration:  1) Needed tell 'make vendor_hwselect...' to run kernel from SDRAM. Running from CFI causes uClinux to not boot.  2) Reset vector in SOPC builder is set to base of my CFI flash.  3) I didn't touch the Exception Vector (still in onchip_mem) at offset 0x20.  4) I kept my config.c as default. I may come back to this and find out what effect it really has on uClinux. If it does double the amount of flash uClinux can see I'll change it. For now, everything works fine.   When the project I'm working on is done and I have some time to mess around some more, I hope to update many of the articles I've come across with information that will help DE2-70 users strugling to figure things out.