General SOPC and Quartus

[Altera_Forum]

First a little background: 

 My company recently sponsored 3 days of Quartus training for my team (it was good training). Following the training the engineers on my team were given different tasks to further their knowledge. We also have decided to get the Nios training brought in. Combined experience with my team is over 80 yrs of FPGA, ASIC, and Embedded System development.  As a development team we are moving from using a different FPGA vendor and separate processor to an Altera device and NIOS II, so we will be migrating a large amount of code. The software team likes Nios, the HDL team likes the Avalon bus, so we should all be happy.  Now my task was to investigate SOPC builder, custom component creation, and basically what it is going to take to make the migration happen. Unfortunately my experiences with SOPC builder has made me very concerned with this migration. I took both of the On-Line SOPC classes and as long as I was duplicating the examples all went well, but when I began taking our own custom code and making the modifications to port into SOPC things have gone very poorly.  As a group we are very concerned about the *_hw.tcl files that will be generated for each block on the bus implemented in the SOPC. We are also concerned with the *.vhd code that is being generated, as it seems to be inefficient and potentially hard to debug in case of errors.   In general it seems to us that we are placing a lot of faith and trust in SOPC and Quartus to the bus infrastructure. Keep in mind the experience level of this team. We understand that there are advancements in tools, and new methods for getting things done. Unfortunately the migration to the Altera device is to be completed in 4 months. My recent experience and struggles with the tools does not make this likely.  So, the Question I would ask the forum is trust the tools or trust our experience to get it done right? We can instantiate all of the components including Nios and our misc. components in Quartus and structure the code to operate as Avalon-MM and -ST with the thought that Quartus will recognize the structure and infer all of the resources properly or let the tools do all of that for us with the belief that we will never have to touch the tool generated files.  I welcome any thoughts and opinions.  Brett

[Altera_Forum]

Wow, this is a lot to answer via a forum post. I'd almost rather talk to you on the phone. 

 Let's see.  I've been using SoPC Builder for several years now. Honestly I love it. I fell in love with it the first time I used it. Now I'm going to sound like a fanboy but I will say that I use both Xilinx (including EDK and microBlaze) and Altera. My bias has developed out of usage experience. I should also state that my designs typically have a heavy amount of logic outside of SoPC builder and a heavy amount of logic within SoPC builder.  Lets state some simple truths: 1 - Between custom IP and generated IP ... You will always be able to write more efficient code than what you'll get from generated IP. A few reasons for this:  . a - Generated IP is designed to be all things to all people. It has to be generic to be useful for multiple audiences. This results in inefficiencies.   . b - A human will generally make more intelligent decisions than an algorithm. So for example, creating the memory map of your SoPC system. You are going to do a better job than SoPC builder is going to do.  2 - Using SoPC Builder implies that you are going to trust it to create reliable, bug-free code. Yes that means letting go of the control. The only way you can feel good about this is through positive experience that the tools produce reliable designs. You don't have that experience yet. However, I do, and a whole lot of other users (including those on the forum) do.  3 - The reason that you are going to take the risks listed in 1 & 2 is to gain some benefit. What are those beneifits?   . a - SoPC builder allows you to spend your time architecting the system rather than performing the busy work of actually piecing it together. You connect components with the click of a button rather than manually entering.   . b - SoPC Builder provides an infrastructure and design mentality that allows your design team to collaborate and design more quickly. Your interfaces are already defined (Avalon-MM, Avalon-ST). Your tools are defined (SoPC Builder, Quartus). The hardware is now very tightly integrated with the software allowing software and hardware to collaborate more easily.   . c - You're hoping to get to market faster and at a lower development cost.   . d - Using the NIOS processor you've just added the ability to add almost any custom hardware acceleration or integration to your processor within the FPGA. No re-spinning the board, no adding external chips. And it becomes a whole lot easier to test and debug your HDL code with that NIOS processor sitting in there.   . e - Removing the external CPU from the board removes a whole layer of design work for both hardware and software. You get to remove all the power supplies associated with the external CPU. The MTBF rating on your board improves because of diminished part count. You're more likely to get your prototype board right the first time because it's all FPGA code at this point. You probably saved power with the NIOS over the external CPU. You don't have to worry about the external CPU going end-of-life anymore.  . f - The components you create for SoPC builder can be easily reused in any other SoPC design. This makes it easy to pass components around to other engineers and easy to leverage in your next design.  . g - The avalon bus provides flexiblity in interfacing to memory and components that quite frankly would take you a very very long time to achieve on your own.   Now my personal experiences: 1 - In general, SoPC builder and all of the generated design code and IP has been rock solid. I rarely ever have a need to poke into Altera's generated code or IP blocks. In general, I fully place my trust in the system to do what I'm telling it to do. Keep in mind also that you have full access to any of your code that you put into the system.  2 - Altera's tools (Quartus, SoPC builder, and NIOS) are ... freakin' awesome right now. Maybe that'll change at some point but for right now, they're really on top of their game. It's a joy to use Quartus. You get more information from that tool about your design than you ever even knew was possible.  3 - If you know what you are doing, SoPC Builder can produce very efficient code. I'm willing to pay the price for a little code bloat because I get to market faster, the design is easier to modify, easier to maintain. And honestly if you're changing from brand X fpgas, you've got room to spare anyway because you're going to get better resource utilization from an Altera part.  4 - Engineering has gotten so broad and our products have gotten so complex that I just don't have the time to do things the old way anymore. I can't spend the time piecing together the bus architecture. Click-Click done for me.  Now all these things being said. I would definitely recommend that you read all the available documentation. The more you understand about how the system works, the more you'll feel like your able to control it and the more comfortable you'll be with its results.  Absolutely DO NOT take the approach of piecing the NIOS and everything together separately. This is ludicrous. The benefit of the NIOS processor is not in the NIOS processor. The benefit lies in SoPC builder, the Avalon Interconnect Fabric, and the tight integration between hardware and software. If you are not going to take advantage of these, then drop the NIOS altogether. It's not worth it. Go pick some other processor.  My recommendation: Take a step out into the unknown. Let go. If you're like me you'll wonder how you ever lived without it. You'll start putting a NIOS in every design. You've got everyone on the forum to help you. Altera's probably willing to sleep in your office to get a design win so they'll support you. You'll start blowing everybody away with how fast you get the hardware design done.  Oh man that was a mouthful. Let me take off my cheerleader outfit. If you want to talk on the phone to specifically address your concerns, just send me a private message with your phone number.  Jake  P.S. What's wrong with the "_hw.tcl" files? I'm pretty fond of them. You should have seen they way they used to do things prior to 7.1.

[Altera_Forum]

Haven't posted enough to allow for a pm.

[Altera_Forum]

jake is absolutly right. 

 just to give you an impression about my experience with altera, quartus nios ..  when we compared the different fpga companies a couple of years ago, while moving from ASIC design on SUNs with Cadence tools, with their tools and components, it was realy interesting that from a component view is doesn't matter which manufacture you choose the price is more or less equal, but the tools and design flow is so different. at the time altera and the "X..." company was like summer and winter. we deceided to go with Altera ( we would be more than mad not to do so ) as the tools and the idea behind sopc builder, avalon switch fabric was like a dream come true. yes it took a while to get behind the idea of how the tools and the functionality are intended to be used. and there were some pitfalls and of course bad bugs in the past. but what we first noticed was the ease of use of the sopc builder and the component editor. integrating ip functionality inside an sopc ip module and some outside is realy easy and now a days i realy trust sopc builder. we have designs with 9 avalon masters and 12 slaves and the avalon switch fabric does all the abitration. reusability of IPs is easy and now we have a plattform system where all fpga design are based on the same sources with different combinations. even the ability of the nios that the software is compatible between NiosII-e up to -f is used as well as the custom instructions. desinging custom IPs is also not a problem once you have understood the avalon interface. the streaming interface is great, no need to think about the data exchange between IPs with different clock cycles to compute the data.  one important thing to mention, at least for me, if you have a question or problem use the MySupport if you do not find the answer here at the forum or the web page.   i realy like the tools and the design flow.   as jake said, take that step and you will notice how fast you can get and will not go back.  Michael  BTW: @Jake could you post a photo .. you in cheerleader outfit ;-)

[Altera_Forum]

Another note - From what I'm seeing on the forum I think I would recommend that you don't use the 10.0 tools yet. Stay with 9.1 until 10.0 gets shaken out. That's just my opinion. 

 Michael,  I'd better spare the innocent forum users from seeing the cheerleader photo. The thought alone ought to be frightening enough. :)  Jake

[Altera_Forum]

yes it seems that 9.1 SP2 with Patch 2.46 (via MySupport if you are using EPCS as configuration device ) is the best Version to work with. 

 Jake  i am watching "Little Britain" and i love Waldorf & Stadler, do you still think something could frightening me ? Stadler. "the show was excelent" Waldorf: "yes, until it had started"

[Altera_Forum]

Jake/Michael, 

 Thanks for the cheerleading and words of support. One of the biggest challenges I face is one of time. The system needs to be in place within 8 weeks for first HW.  I am going to give it a shot and try again but a slightly different approach. The magnitude of the number of slave blocks and all of the changes that are going into this change is huge. We are taking 2 lattice FPGAs w/ two ARMs and combining into a single Arria II with a Nios. I believe I will attempt an Avalon Slave bridge to the custom code to just get the system moving. If that is successful we at least will have a working system in 8 weeks, after which we have another 8 weeks to start porting individual slaves one at a time.  Brett

[Altera_Forum]

On another note concerning 10.0 vs 9.1 sp2, we have to stay in 10.0. 9.1 does not support the device we are using. 

 Brett

[Altera_Forum]

Pinscore... 

 after we did the decicion to go with altera and startet a new product family from scratch with nios , new RTOS, digital signal processing lots of FIR, everything new, as well as full custom housing, different host protocols and interfaces from serial, ethernet, profibus and now profiNet ..... 7 new devices were produced and running on an international sales meeting within 3 Months. so i knew it is possible with altera.  So have fun !

[Altera_Forum]

At them moment, "fun" isn't in the vocabulary. I am going to be the only champion amongst a group of 7, which includes management. It is going to be a long 8 weeks I feel.

[Altera_Forum]

and YOU are going to be the winner ! with this in your mind, it's fun !

[Altera_Forum]

Thanks Mike!