Code for 24 mhz to 434Khz..

[Altera_Forum]

Hi .. 

 I have made one code for 24 mhz to 434Khz (Frequency divider)..  Actually in my project, i have 24 Mhz clock freqency and i want to convert it into 434 Khz...  My code is..  Library IEEE; Use IEEE.std_logic_1164.all;  Entity FA is port(clk :in bit; clkout : out bit); End Entity FA;  Architecture FA_calc of FA is  begin process(clk) variable cnt : integer range 0 to 28; begin if(clk'event and clk='1') then if(cnt = 28 ) then  clkout<='1'; else cnt := cnt+1; clkout<='0'; end if; end if; end process;  End Architecture FA_calc;  Is it correct or not ??  ie cnt should be 28 or 56 ??  Thanks a lot..

[Altera_Forum]

Hi Satish, 

 You can create a simple testbench and run modelsim simulation for your code to see if it works as is expected. Or alternatively, you could create a test vector in Quartus II and do simulation in Quartus II as well.

[Altera_Forum]

It would be better to use a clock enable instead of a divided clock. If you are going to use the divided clock, it is best for that clock to be global with no synchronous paths going to or from that clock domain. Search this forum for "clock enable" to find my posts with comments on this. http://www.alteraforum.com/forum/showthread.php?t=680 in particular has someone else's code example and my comments on changing it from a divided clock to a clock enable solution.

[Altera_Forum]

I saw your related post at http://www.alteraforum.com/forum/showthread.php?p=2411. If you need a true 434 kHz clock waveform going to an output device pin and also need internal logic running at 434 kHz, you can still use a clock enable for the internal logic. If that internal logic has to be synchronous to whatever is outside the FPGA using the 434 kHz clock driven out by the FPGA, then it might be better to use the true 434 kHz clock waveform internally. However you do this, be careful with any paths crossing synchronously between clock domains.

[Altera_Forum]

Why do you not use a PLL and generate the internal and external freq.s in thge PLL device?

[Altera_Forum]

PLLs can generate 10 or 15 MHz minimum (for cyclone devices). The minimum output frequency of PLL varies with the targeted device. I think it would not be possible to get below 1 MHz using Altera device PLL. Hence, divide counter should serve the purpose in this case (for 434 KHz).

[Altera_Forum]

Did I miss a reference to the Cyclone part above? 

 I did a test case in the megawizard using the Stratix part which will go down to .3 MHZ (300 KHz).  Good catch.

[Altera_Forum]

Hi Avatar, 

 I don't know which is the target device here, but I just quoted an example of cyclone device to indicate PLL Input/Output frequency limitation, which I faced with cyclone device. I just wanted to indicate that target device will also affect the design if PLL is to be used. I also did a similar test for megawizard (just like you did) and apparently Altera is improving on the PLL limitations. With new devices like Cyclone III/Stratix III, you can get as low frequencies as 1.5 KHz (0.0015 MHz)! (Not verified in the Hardware though, but it should work as Megawizard is not restricting this setting).  This is also new for me and worth taking note of. :)  Thanks BD

[Altera_Forum]

--- Quote Start ---  Hi ..  I have made one code for 24 mhz to 434Khz (Frequency divider)..  Actually in my project, i have 24 Mhz clock freqency and i want to convert it into 434 Khz...  My code is..   --- Quote End ---    How close would you like to reach to 434k? Dividing by 56 is not too accurate (?)  Maybe you try this :  24000000,00 0,00000004167 434000,00 0,00000230415 55,29954  2,00  27,6498 !!!!!   28 0,00000116667 27 0,00000112500 28 0,00000116667 27 0,00000112500 28 0,00000116667 27 0,00000112500 28 0,00000116667 27 0,00000112500 28 0,00000116667 28 0,00000116667 -- ----------------- 10 0,00001150000  -> 434782,61  Or do a kind of modulation, when jitter does not matter:  Start with 217 and keep adding 217 as long as 6000 are not reached yet, then toogle to output and decrease the number by 6000. In average you will obtain the required factor of the given freqs.