Output Pins stuck at VCC or GND

[Altera_Forum]

Hi all. I've just finished writing and simulating a program which functions as a calculator.. However upon compiling the program, there is this warning which says: 

 "Output Pins stuck at VCC or GND".  Just so you all know I'm still relatively new to VHDL and am not particularly well versed yet. I wish to know how can I solve this problem. The pins are actually 2 pins which I intend to interface with a Seven Segment Display. And both pins are stuck at VCC, therefore permanently lighting those two LEDs.   I have two questions:  a) Why are those pins stuck at VCC when I did not assign any pins yet. b) How do I avoid this problem.  Thanks for those who can help.

[Altera_Forum]

Hi, 

 since you haven't yet assigned then don't worry(the fitter felt free and chose to tie them up to vcc). Once you drive your outputs then the fitter will obbey your assignment.  The fitter actually follows default (unused pins assignment)

[Altera_Forum]

--- Quote Start ---  Why are those pins stuck at VCC when I did not assign any pins yet.  --- Quote End ---  Very unlikely. You get this message for pins, that have been assigned but are not driven by logic. Either you connected no logic to the pin or the connected logic has a constant output. The purpose of the warning is making you check for logic that has unintentional constant output.

[Altera_Forum]

If you mean by "assign" the pin assignment rather than logic drive then what might have happened is that the fitter was left free to assign pins as it liked. In that case possibly you are driving some outputs high which the fitter chose to assign them to those pins. user-unassigned project pins can sometimes be damaging in real systems, so beware...

[Altera_Forum]

My previous statement wasn't fully correct. Pins not assigned to a design top port are treated according to the designs unused pin rule, but not reported with the said stuck-to message. The message appears with port pins driven intentionally or unintentionally by a constant driver. If the output is expected not to have constant output, the logic should be corrected.

[Altera_Forum]

Hi all. Thanks for all your help. I looked through my code and it seems that I did assign logic 1 to those pins. Thanks again :)

[Altera_Forum]

Hi,what about "the input pins do not drive the logic" ?In reality,I do have used them in my project.

[Altera_Forum]

Quartus will optimize your design and remove unnecessary logic. 

If you have a input pin but, somehow, your design's behavior does not depend on it's value, Quartus will optimize it away.  If this is not the intended design, then you have an error in your logic.

[Altera_Forum]

--- Quote Start ---  In reality,I do have used them in my project.  --- Quote End ---  May be. But after fitting the design, there was no logic. Any superfluous logic, that doesn't connect to output pins, is automaticly removed.

[Altera_Forum]

In my project I use a "component" sentence.But ,when I compile the component only ,that pin do work(the warning disappear,I can see its route),it'll have no routes if it connects to upper structure.So why?

[Altera_Forum]

Hard to say. 

I suggest that you simulate your design. You should see that it does not react to those input pins that do not drive logic. Then try to find out why.

[Altera_Forum]

OK,Now I just write the codes down from a book.After compilation ,it also shows the warning about input pins donot drive logic ,out output pins are stuck at GND or VCC.When I looked into the RTL, saw a circuit seems right,but in MAP VIEWER,there were nothins other than input output pins.What's wrong?

[Altera_Forum]

--- Quote Start ---  Now I just write the codes down from a book.  --- Quote End ---     --- Quote Start ---  in MAP VIEWER,there were nothins other than input output pins.  --- Quote End ---   You may want to show a complete example, that demonstrates the said issue.

[Altera_Forum]

Here is complete example.Now just to find the errors,everybody,maybe helpful to all of us. 

--receiver entity Library ieee; use ieee.std_logic_1164.all; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity uart_receiver is   port(RxD,bclkX8,sysclk,RDRF,RST_B:in std_logic;  RDR:out STD_LOGIC_VECTOR(7 downto 0);  SETRDRF,WRONG:out std_logic); end uart_receiver; architecture rcvr_behavior of uart_receiver is TYPE STATETYPE IS (IDLE,START_DETECTED,RECV_DATA); SIGNAL STATE,NEXTSTATE:STATETYPE; SIGNAL RSR:STD_LOGIC_VECTOR(7 DOWNTO 0);--RECEIVE SHIFT REGISTER SIGNAL CT1:INTEGER RANGE 0 TO 7;--INDICATES WHEN TO READ THE RXD INPUT SIGNAL CT2:INTEGER RANGE 0 TO 8;--COUNTS NUMBER OF BITS READ SIGNAL INC1,INC2,CLR1,CLR2,SHFTRSR,LOADRDR:STD_LOGIC; SIGNAL BCLKX8_DLAYED,BCLKX8_RISING:STD_LOGIC; BEGIN  BCLKX8_RISING<=BCLKX8 AND NOT BCLKX8_DLAYED; --INDICATES THE RISING EDGE OF BITX8 CLOCK  RCVR_CONTROL:PROCESS(STATE,RXD,CT1,CT2,BCLKX8_RISING,rdrf)  BEGIN  --RESET CONTROL SIGNALS  INC1<='0';INC2<='0';CLR1<='0';CLR2<='0';SHFTRSR<='0';LOADRDR<='0';  SETRDRF<='0';WRONG<='0';  CASE STATE IS  WHEN IDLE=>  IF(RXD='0') THEN  NEXTSTATE<=START_DETECTED;  ELSE NEXTSTATE<=IDLE;  END IF;  WHEN START_DETECTED=>  IF BCLKX8_RISING='0' THEN  NEXTSTATE<=START_DETECTED;  ELSIF RXD<='1' THEN  CLR1<='1';NEXTSTATE<=IDLE;  ELSIF CT1=3 THEN  CLR1<='1'; NEXTSTATE<=RECV_DATA;  ELSE INC1<='1';NEXTSTATE<=START_DETECTED;  END IF;  WHEN RECV_DATA=>  IF BCLKX8_RISING='0' THEN  NEXTSTATE<=RECV_DATA;  ELSE INC1<='1';  IF CT1/=7 THEN --WAIT FOR 8 CLKCL CYCLES  NEXTSTATE<=RECV_DATA;  ELSIF CT2/=8 THEN  SHFTRSR<='1';INC2<='1';CLR1<='1';--READ NEXT DATA BIT;  NEXTSTATE<=RECV_DATA;  ELSE   NEXTSTATE<=IDLE;setrdrf<='1';CLR1<='1';CLR2<='1';  IF RDRF='1' THEN WRONG<='1';  else LOADRDR<='1';  END IF;  END IF;  END IF;  END CASE;  END PROCESS; RCVR_UPDATE:PROCESS(SYSCLK,RST_B) BEGIN  IF RST_B='0' THEN STATE<=IDLE;BCLKX8_DLAYED<='0';CT1<=0;CT2<=0;  ELSIF SYSCLK'EVENT AND SYSCLK='1'THEN  STATE<=NEXTSTATE;  IF CLR1='1' THEN  CT1<=0;  ELSIF INC1='1' THEN  CT1<=CT1+1;  END IF;  IF CLR2='1' THEN  CT2<=0;  ELSIF INC2='1' THEN  CT2<=CT2+1;  END IF;  IF SHFTRSR='1' THEN RSR<=RXD & RSR(7 DOWNTO 1);  END IF;  IF LOADRDR='1' THEN --UPDATE SHIFT REG.  RDR<=RSR;  END IF;  BCLKX8_DLAYED<=BCLKX8;--BCLKX8 DELAYED BY 1 SYSCLK  END IF; END PROCESS; END RCVR_BEHAVIOR;   following are warnings Warning: Output pins are stuck at VCC or GND  Warning (13410): Pin "RDR[0]" is stuck at GND  Warning (13410): Pin "RDR[1]" is stuck at GND  Warning (13410): Pin "RDR[2]" is stuck at GND  Warning (13410): Pin "RDR[3]" is stuck at GND  Warning (13410): Pin "RDR[4]" is stuck at GND  Warning (13410): Pin "RDR[5]" is stuck at GND  Warning (13410): Pin "RDR[6]" is stuck at GND  Warning (13410): Pin "RDR[7]" is stuck at GND  Warning (13410): Pin "SETRDRF" is stuck at GND  Warning (13410): Pin "WRONG" is stuck at GND Warning: Design contains 5 input pin(s) that do not drive logic  Warning (15610): No output dependent on input pin "bclkX8"  Warning (15610): No output dependent on input pin "RDRF"  Warning (15610): No output dependent on input pin "sysclk"  Warning (15610): No output dependent on input pin "RST_B"  Warning (15610): No output dependent on input pin "RxD"

[Altera_Forum]

Thanks for paying attention to.The warnings are not complete.Here is another important one. 

Warning: No paths found for timing analysis

[Altera_Forum]

--- Quote Start ---  Thanks for paying attention to.The warnings are not complete.Here is another important one. Warning: No paths found for timing analysis  --- Quote End ---    Hi,  I did some runs of your code and found that when I choose e.g. StratixIII I did not get your Warnings. It looks to me that we found a bug in Quartus. I have the project attached. I will contact Altera to solve this issue.  Kind regards  GPK

[Altera_Forum]

Hi&#65292;pletz! Did you try another device family like cyclone ii? Just now ,I try the stratix ii,those warning disappear indeed. How this happened? Should that possible when one device family works well ,another one be omitted all of the connection?

[Altera_Forum]

--- Quote Start ---  Hi&#65292;pletz! Did you try another device family like cyclone ii? Just now ,I try the stratix ii,those warning disappear indeed. How this happened? Should that possible when one device family works well ,another one be omitted all of the connection?  --- Quote End ---    Hi,  I'm not sure why this happens. In my point of view it is a bug in Quartus. Maybe some Quartus defaults are different when using different FPGA families. None of the cyclone familie works. I have a service request send to Altera. I will keep you informed.  Kind regards  GPK

[Altera_Forum]

I don't think it's a Quartus bug. Actually the "RESET CONTROL SIGNALS" related action in the asynchronous process defines ambigious logic. You have e.g. 

LOADRDR<='0'; -- WHEN RECV_DATA => -- NEXTSTATE<=IDLE; -- LOADRDR<='1'; In other words LOADADR is set for "no time", so the output data are never written to the output port. Similar things happen most likely to the other outputs. I didn't check, how the design result with Stratix III behaves, but it can't be as intended, I fear.

[Altera_Forum]

--- Quote Start ---  I don't think it's a Quartus bug. Actually the "RESET CONTROL SIGNALS" related action in the asynchronous process defines ambigious logic. You have e.g. LOADRDR<='0'; -- WHEN RECV_DATA => -- NEXTSTATE<=IDLE; -- LOADRDR<='1'; In other words LOADADR is set for "no time", so the output data are never written to the output port. Similar things happen most likely to the other outputs. I didn't check, how the design result with Stratix III behaves, but it can't be as intended, I fear.  --- Quote End ---     Hi FvM,  but why behaves the synthesis so differently ?  Kind regards  GPK

[Altera_Forum]

Interesting question. I really don't know.