LVDS Assignment in Quartus

[Altera_Forum]

Hi, 

I am using Quartus II 7.2 for programming a Stratix III device. I have an 8 channel (12 bit) LVDS input that I wish to deserialize and 2 LVDS clocks. I believe the megafunction for deserialization does not work for 12 bit data. Hence I will do it using a verilog program.    I want to know how I can assign an LVDS input pin to a variable. As we know that each LVDS input has a p and an n pin. Do I need to assign them to a single variable? If so, how?   As you might have guessed I am a beginner in FPGA programming.   Thanks a lot  Jatin Pasrija

[Altera_Forum]

LVDS I/O are usually represented by one signal in ports and pin assignments, the positive pin is assigned acting for both. The negative pin is assigned automaticly by the fitter. 

 LVDS I/O with Startix III is connected to dedicated SERDES hardware, but it can be bypassed. I didn't try, but I assume, it can be done by simply acessing the input in regular logic directly rather instantiating a LVDS receiver.  To receive 12 Bit serial data, it's possible to use the SERDES hardware as well. e. g. by receiving 2 x 6 bit with double word rate and multiplexing the data to 12 bit. The dedicated LVDS receiver would use the source frame clock only and generate the bitclock from a PLL. This gives more flexibility in adjusting the clock phase than using a fixed bit clock. Lower LVDS rates up to 600 MHz could be also received through DDIO (double data rate) registers, as done in Cyclone series, that has no dedicated SERDES hardware.  By utilizing an ADC custom or test pattern, the LVDS phase could also be adjusted with DPA. This may be interesting particularly for higher LVDS data rates.

[Altera_Forum]

In case that you still want to do it in verilog, you will see the LVDS pin as usual pin in your verilog. You do not need to worry about the n-pin. As long as you assign the pin as LVDS in assignment editor, Quartus will automatically make the pin as LVDS at the IO buffer. While in your verilog code, you will see it as a single pin. By the way, verilog does not take care of the IO standards.

[Altera_Forum]

Have you tried using the ALTLVDS Megafunction? this will make your life so much easier.

[Altera_Forum]

The problem is the deserialisation factor of 12, unfortunately unsupported by Stratix III. With Stratix, this limitation is by SERDES hardware. I had similar problems with a Cyclone III 14 bit receiver. With Cyclone soft SERDES blocks, maximum of 10 bit is just an arbitrary Megafunction limitation.

[Altera_Forum]

As previous posts said, it is OK to have only the "p" leg of a differential pin pair in the source file and let the Fitter automatically create the pin for the "n" leg and place it in the correct location. However, you have the option of including both the "p" and "n" legs in your source file for Stratix III and Cyclone III. Here is the Help page for the primitive that lets you do this with input pins: 

   --- Quote Start ---  ALT_INBUF_DIFF Primitive   --------------------------------------------------------------------------------  The ALT_INBUF_DIFF primitive allows you to name and connect positive and negative pins when a differential I/O standard is applied to an input pin. This primitive allows you to do the following:  Make a location assignment  Make an I/O standard assignment  Enable bus-hold circuitry  Enable a weak pull-up resistor  Make an on-chip termination (OCT) assignment to an input pin from a lower-level entity  This primitive is available for Cyclone III and Stratix III devices only.  ...   Verilog HDL Example Instantiation:  module test_inbuf_diff (in, in_n, out); input in,in_n; output out; ALT_INBUF_DIF inst1(.i(in), .ibar(in_n), .o(out)); defparam inst1.io_standard = "LVDS"; defparam inst1.location = "IOBANK_1"; defparam inst1.weak_pull_up_resistor = "off"; defparam inst1.enable_bus_hold = "off"; endmodule  --- Quote End ---  

[Altera_Forum]

Hi, 

I decided to go with LVDS DESER megafunction to deserialize into 2x6 bitstream and them multiplex it into 12 parallel signals (i have yet to figure that out though). The problem with alt_lvds is that it is not aligning the data properly. I want the first bit to be registered at the positive edge of the clock. Whereas the megafunction registers the input at positive edge to be the third bit. I tried giving phase difference in the options available in the megafunction window. Tried all the phase differences 45,90,180,270....but the output still remains the same.. Am I missing something here. Attached is a pic of the output.   Jatin

[Altera_Forum]

Does ALT_INBUF_DIF have a VHDL implementation available for use as a component? 

 Or would it just be:  component ALT_INBUF_DIF  port  (  i : in std_logic;  ibar : in std_logic;  o : out std_logic  ); end component;    BR

[Altera_Forum]

Brad wrote: 

"it is OK to have only the "p" leg of a differential pin pair in the source file and let the Fitter automatically create the pin for the "n" leg and place it in the correct location."  So, no reference to the "n" signal should appear in the logic or in a pin assignment? Just make the pin assignment to "p" pin with an LVDS type and couple that with the logic level signal in the top level source file?  What about for outputs, does it work the same way just in reverse? Make the "p" pin assignment, couple it with the logic level signal name and QII will pick-up the "n" for you?  Thanks in advance, BR

[Altera_Forum]

--- Quote Start ---  Does ALT_INBUF_DIF have a VHDL implementation available for use as a component?  --- Quote End ---     Your question is answered on the same Help page I copied from before. More from that Help page:    --- Quote Start ---  VHDL Component Declaration:  The following VHDL component declaration is located in the VHDL Design File (.vhd) ALTERA_PRIMITIVES_COMPONENTS.VHD located in the <Quartus II installation directory>\libraries\vhdl\altera directory.   component alt_inbuf_diff generic( io_standard : string := "NONE"; location : string := "NONE"; enable_bus_hold : string := "NONE"; weak_pull_up_resistor : string := "NONE"; termination : string := "NONE"; port( i : in std_logic; ibar : in std_logic; o : out std_logic); end component;  VHDL LIBRARY-USE Declaration:  The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration.  LIBRARY altera; USE altera.altera_primitives_components.all;  --- Quote End ---  

[Altera_Forum]

--- Quote Start ---  Brad wrote: "it is OK to have only the "p" leg of a differential pin pair in the source file and let the Fitter automatically create the pin for the "n" leg and place it in the correct location."  So, no reference to the "n" signal should appear in the logic or in a pin assignment? Just make the pin assignment to "p" pin with an LVDS type and couple that with the logic level signal in the top level source file?  What about for outputs, does it work the same way just in reverse? Make the "p" pin assignment, couple it with the logic level signal name and QII will pick-up the "n" for you?  --- Quote End ---     The standard Quartus method of dealing with differential signals--both inputs and outputs--is to have a single signal as a top-level port and to use that signal name in assignments. If the top-level port is called my_diff_pin, Quartus will use my_diff_pin for the "p" leg and my_diff_pin(n) for the "n" leg. You use my_diff_pin in assignments. When you are working in the Pin Planner, you might see a location assignment for my_diff_pin(n) appear, but that assignment is not necessary.  The primitives like alt_inbuf_diff were added to give users the option of including top-level ports for both the "p" and "n" legs for Cyclone III, Stratix III, and I expect (even though it isn't on the help page yet) Stratix IV.

[Altera_Forum]

I tried this in QII and it seems to work fine after I cut out all mentions of my "n" signals. QII picks up the n signal and creates it on the differential pin pair.  

 I am used to using a primitive to instantiate diff IO pairs like that, using IBUF_LVDS or OBUF_LVDS. I would imagine Altera gets lots of requests for the prims. lots of extra typing though....  Now, if I can just figure out why QII will not allow me to have LVDS outputs, I'll be good to go.  Thanks for your help Brad, BR

[Altera_Forum]

--- Quote Start ---  I am used to using a primitive to instantiate diff IO pairs like that, using IBUF_LVDS or OBUF_LVDS. I would imagine Altera gets lots of requests for the prims.   --- Quote End ---     As I said in my previous post, the primitives like alt_inbuf_diff were added to give users the option of including top-level ports for both the "p" and "n" legs.

[Altera_Forum]

Hello Jatinp, 

 I checked your results in Quartus simulator, cause I have no Stratix III board available. I had a 2x7-Bit deserializer setup, that I used with an AD9259, Cyclone III and derialization in LE. The sample rate is 32 MHz in this case. I changed it to a Stratix III 7-Bit LVDS receiver with this Megafunction parameters: common_rx_tx_pll => "OFF", deserialization_factor => 7, enable_dpa_mode => "OFF", implement_in_les => "OFF", inclock_data_alignment => "UNUSED", inclock_period => 31250, inclock_phase_shift => 0, input_data_rate => 448, intended_device_family => "Stratix III", lpm_hint => "CBX_MODULE_PREFIX=RX", lpm_type => "altlvds_rx", number_of_channels => 4, outclock_resource => "AUTO", registered_output => "OFF", use_external_pll => "OFF", rx_align_data_reg => "RISING_EDGE" I found, that the input data had to be delayed by 4 bitclocks to get correct word alignment.  I understand that your results are also from simulation. Have you the opportunity to validate the alignment with Stratix III hardware?   I have been using hardware SERDES before with Arria GX, but in a design with DPA. So the word alignment was achieved automaticly without thinking about it.  I suspect, that Stratix III LVDS receiver may require some pulses at the data_align input to achieve the specified alignment of LVDS frame with inclk rising edge. Another option is to use an external PLL and specify an appropriate phaseshift for the LVDS clocks. The inclock_phase_shift in LVDS receiver Megafunction has an adjustment range of a bitclock interval only. But you can see in PLL parameters report, that the Megafunction is using a multiple bit clock phase shift for the internal LVDS slow clock.  Regards, Frank